Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
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Quartus Prime (Lite Edition): timing violation signals on Netlist

Honored Contributor II

How can I look signals out that cause timing violations (setup/hold) on Netlist. 

If there are some timing violations on some signals, I can put FFs between those signals to prevent setup/hold timing violations. 

My question is how can I figure it out where is the right place to put FFs? (in Quartus Prime) 


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Honored Contributor II

Use the Timing Analyzer (aka TimeQuest). From the Quartus Compilation report in the Timing Analyzer folder, right-click the clock domain(s) in the summary reports that are failing timing and select Report Timing. This will create a detailed timing report in the timing analyzer. You can then right-click a failing timing path and cross-probe to the Chip Planner or the Technology Map Viewer to get more detail about the failing path(s).