Quartus Prime (Lite Edition): timing violation signals on Netlist

[Altera_Forum]

How can I look signals out that cause timing violations (setup/hold) on Netlist. 

If there are some timing violations on some signals, I can put FFs between those signals to prevent setup/hold timing violations. My question is how can I figure it out where is the right place to put FFs? (in Quartus Prime)  Thanks.

[Altera_Forum]

Use the Timing Analyzer (aka TimeQuest). From the Quartus Compilation report in the Timing Analyzer folder, right-click the clock domain(s) in the summary reports that are failing timing and select Report Timing. This will create a detailed timing report in the timing analyzer. You can then right-click a failing timing path and cross-probe to the Chip Planner or the Technology Map Viewer to get more detail about the failing path(s).