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14943 Discussions

Quartus Prime Lite: Error in WHEN conditional

Altera_Forum
Honored Contributor I
883 Views

This question is very basic, but I just started learning VHDL, and I can't figure out the error.So, I'm using Quartus Prime Lite, and getting error 

 

 

error (10500): vhdl syntax error at package_42.vhd(30) near text "when"; expecting ";" 

 

when compiling the following piece of code.Any ideas what could be wrong? 

 

Thanks! 

 

 

library ieee; use ieee.std_logic_1164.all; package Package_42 is subtype StepType is std_logic_vector(3 downto 0); function Problem_42(a : in std_logic; b :in std_logic; j : in StepType; k : in StepType) return StepType; end; package body Package_42 is function Problem_42(a : in std_logic; b : in std_logic; j : in StepType; k : in StepType) return StepType is variable Step : StepType := "----"; begin Step :="0100" when a = '1' and b = '0' else -- ERROR is HERE!!! j when a = '1'else k when b = '1' else "----"; return Step; end; end package body;  

 

 

 

0 Kudos
3 Replies
Altera_Forum
Honored Contributor I
99 Views

You can't synthesize don't cares: "----". 

 

Also, Step is a variable. It needs to be assigned to a signal to synthesize to hardware.
Altera_Forum
Honored Contributor I
99 Views

"when" can only be used in procedural code in VHDL 2008. Otherwise it is limited to architecture bodies outside of processes only. 

 

Dont cares are perfectly synthesisable, it tells the compiler you really dont care, and allows it to chose what value to take.
Altera_Forum
Honored Contributor I
99 Views

Whoops, you're right. Not sure what I was thinking when I wrote that. Of course don't cares should be synthesizable.

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