Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
Announcements
Intel Support hours are Monday-Fridays, 8am-5pm PST, except Holidays. Thanks to our community members who provide support during our down time or before we get to your questions. We appreciate you!

Need Forum Guidance? Click here
Search our FPGA Knowledge Articles here.
15461 Discussions

Quartus Prime Lite keep hierarchy

Christian_Woznik
697 Views

Hello everyone,

I have a design where I would like the fitter to not optimise between the individual modules but do optimise inside.  So I can not use the global option for that as that would almost double the resource usage.

As I figured out Quartus does not support the VHDL synthesis attributes like syn_sharing but you should use partitions. However incremental compilation is not supported in the Lite version so I need a different option on how to archive that.


Is this function just not supported by the Lite version (something I could just not understand at all since as far as I know all other manufacturers support it) or is there another option on how to archive it in Quartus? 

Best regards
Christian

Edit:
Just to clarify: I do not want incremental compilation. I am entirely happy to just recompile the entire project. I just want to not allow optimisation over the entire logic.

0 Kudos
1 Solution
sstrell
Honored Contributor III
635 Views

Without resorting to design partitioning using Standard, the only thing I can think of is using Logic Lock physical partitioning in the Chip Planner.  I forget if it's available in Lite, though, but I think it is (EDIT: nope, Standard and Pro only).

I think you have to bite the bullet.

View solution in original post

9 Replies
SyafieqS
Moderator
677 Views

Woznik,


Intel do have synthesis attribute like noprune to prevent Quartus from optimizing away register. You may find them more via in Quartus --> New file --> select Verilog/VHDL file --> insert template --> synthesis attribute.




Christian_Woznik
669 Views

Thanks for the reply,

however that is not what I want. I mean I am currently using that statement, which helped in preventing weird optimizations that lead to timing errors (I really do not understand how a compiler optimization could lead to hold time problems, especially with aggressive performance settings while removing registers and free resources available). But in the end it does not help really archive what I want to do. I can not use the statement on all registers as in the end it would archive the same as completely disabling it via the global option and thus not fitting on the FPGA any more.

With Xilinx I can use the keep_hierarchy statement and it fits on similar sized Artix‐7 without any problems. No timing issues or anything. So is there any possibility that I can do the same on the Cyclone V E or am I basically out of luck as long as I do not foot the 3000$ bill?

Best regards
Christian

sstrell
Honored Contributor III
665 Views

It sounds like you want to use the "keep" and "preserve" synthesis attributes instead of noprune.

You don't need incremental compilation to use synthesis attributes.  Incremental compilation just tells the compiler to not touch a part of your design that's already compiled (locked down essentially).  It has nothing to do with optimizing away logic.

SyafieqS
Moderator
656 Views

Christian,


You may need to look at keep and preserve syn_attribute as link below. Maybe that's what you are looking for


1.Keep

https://www.intel.com/content/www/us/en/programmable/quartushelp/17.0/hdl/vlog/vlog_file_dir_keep.ht....


2.Preserve

https://www.intel.com/content/www/us/en/programmable/quartushelp/17.0/hdl/vlog/vlog_file_dir_preserv...



Christian_Woznik
650 Views

Thanks for the reply.

Well it is not exactly what I want. I am currently using that and it helped with the timing problems. But it cuts down on the optimisation and thus really increases the required resources.

With Vivado you have the KEEP_HIERARCHY attribute which basically does exactly what I want to do.

As you may have seen in my other questions I am implementing a neural network via shiftw in the FPGA.  I have the network structured by layers with each layer having their own controls.

If I do not use any attributes Quartus merges all the controls and thus creates very long signal path, it literally goes over the entire FPGA. If I use Vivado with keep_hierarchy it groups the individual layers with the controls on the FPGA and thus archives a lot better timing while not increasing resource use dramatically as it can still optimize quite a bit inside the layers.


Just disabling the merging and optimizations of the controls entirely is not an easy option. There are quite a lot of duplicates and I thought Quartus would do a better job than I can do myself.  If I currently disable the optimization for the controls it just blows up my design by a factor of about 2 making it way to big for the FPGAs I have at hand.

I did somewhat combat it with the keep attribute but it still is a lot worse in both timing and resources than just the simple attribute with Vivado.

So is there any way I can archive something like that without having to try to optimize the controls by hand and then using the keep attribute?

Best regards
Christian

sstrell
Honored Contributor III
636 Views

Without resorting to design partitioning using Standard, the only thing I can think of is using Logic Lock physical partitioning in the Chip Planner.  I forget if it's available in Lite, though, but I think it is (EDIT: nope, Standard and Pro only).

I think you have to bite the bullet.

Christian_Woznik
636 Views

Ok thank you for your answer. I guess I will just drop the Intel FPGA then and just continue with the Xilinx one. A shame that such a feature is locked behind such a paywall with Intel.

I really do not understand why you would do it if you want to sell chips especially if the competition does not do that.

sstrell
Honored Contributor III
618 Views

Cyclone V is a low-end device family at this point.  The Lite version of Quartus lets anybody using the low-end devices get into creating basic designs without having to pay for design software (aka hobbyists and non-production designs).  Anything more complicated requires more advanced features available in Standard and Pro.

Christian_Woznik
611 Views

Well so is the Artix-7 family for Xilinx. I really do not see big selling point for the Cyclone if I compare those two. And Xilinx will also have the new Artix US+ in the free version, so you can get PCIe Gen4 & DDR4 without having to pay for the software licence (once it finally arrives in 2022).

I can understand why you would want to limit certain class of FPGA to the paid version, if you need that kind of system you can pay it, but I do not understand why you have to limit functions even with the series where you offer a free version. I mean the cyclone V also goes up to 300k LE so not really a very small device in the end.

For myself I am just glad that I have bought both boards now for myself.

Reply