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Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
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Quartus Prime Pro 21.3: Platform Designer Problem

GLT1
New Contributor I
675 Views

I'm trying to add a "generic component" into Platform designer that basically just passes Avalon agent signals through in order to access an external device. 

 

Platform designer doesn't report any connection errors, but when I try to generate the design I'm getting the following errors:

 

 

Error: my_qsys: Connection (post-transform) is missing an end point: nios2_gen2_0.data_master->null
Error: my_qsys: Connection (post-transform) is missing an end point: clock_in.out_clk->null
Error: my_qsys: Connection (post-transform) is missing an end point: nios2_gen2_0.instruction_master->null
Error: my_qsys: Connection (post-transform) is missing a start point: null->generic_component_0.avalon_slave_0
Error: my_qsys: Connection (post-transform) is missing a start point: null->nios2_gen2_0.debug_mem_slave
Error: my_qsys: Connection (post-transform) is missing a start point: null->onchip_memory2_0.s1
Error: Internal Error: Cannot generate a system with dangling connections.

 

I've done this sort of thing many times before with Quartus Prime Standard, but have never gotten an error like this. 

 

Attached is a .qar file with an example project that shows the error. Just open the my_qsys.qsys file in the src folder in Platform Designer and click "Generate".

 

Any ideas?

 

Thanks,

Terry

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1 Solution
ShengN_Intel
Employee
567 Views

I try to recreate the example design attached in platform designer.

I found out that if outputenable port under avalon_slave_0 is removed the errors disappear and HDL can be generated. The errors come out if outputenable port is added.

View solution in original post

11 Replies
ShengN_Intel
Employee
644 Views

Hi,

 

Some warnings showed up as well when i try to generate HDL of the sample file provided. Those warnings indicate that some ip files do not exist. Most likely these errors are caused by those missing ip files.

Make sure license is properly installed and not expired as well. And then try to recreate the design file.

 

Thanks.

Best regards,
Sheng

GLT1
New Contributor I
635 Views

Hi Sheng,

 

Are you just getting warnings ? Or errors? 

 

I tried removing and then re-adding all of the components and was able to get rid of the warnings about .ip files not found.  These were apparently just stale .ip files being called out in the .qsf file. 

 

However I am still getting the following errors:

 

Info: Done reading input file
Info: my_qsys: "Transforming system: my_qsys"
Warning: Translator MyComponent_0_avalon_slave_0_translator failed to match interface MyComponent_0.avalon_slave_0
Error: my_qsys: Connection (post-transform) is missing an end point: nios2_gen2_1.data_master->null
Error: my_qsys: Connection (post-transform) is missing an end point: clock_bridge_0.out_clk->null
Error: my_qsys: Connection (post-transform) is missing an end point: nios2_gen2_1.instruction_master->null
Error: my_qsys: Connection (post-transform) is missing a start point: null->MyComponent_0.avalon_slave_0
Error: my_qsys: Connection (post-transform) is missing a start point: null->onchip_memory2_1.s1
Error: my_qsys: Connection (post-transform) is missing a start point: null->nios2_gen2_1.debug_mem_slave
Error: Internal Error: Cannot generate a system with dangling connections.

 

 

I've found that if I only get the errors when the avalon slave in MyComponent is connected to the data_master out of the Nios II processor.  If I export the avalon slave instead, it works fine.    I think that the red-highlighted warning,  which occurs just before the errors, may be the key to fixing this.  But I don't understand what this warning means or how to fix it.

 

Thank you.

Terry

ShengN_Intel
Employee
627 Views

Hi Terry,

 

Same thing here. When I try to export the avalon slave, everything works fine. 

Then I go to generic_component_0/Component Instantiation/HDL/Files and analyze HDL file MyComponent.vhd. After analyzing, i get error states that module not found. Most probably this is the main cause for the errors.

Make sure MyComponent.vhd file exists and working as well as its directory is correct.

 

Thanks.

Best regards,
Sheng


GLT1
New Contributor I
617 Views

Hi Sheng,

 

I've tried doing this two different ways, but am getting the same error both ways.

 

First I tried the generic component (HDL mode) where I read in my VHDL file to create the generic component.  Second, I tried the Component Editor where I also read in my VHDL file to create a component.   Both of these methods result in the same error. 

 

In both of these methods, Platform designer reads in and analyzes the VHDL file, and puts a copy of it down in the ip folder that it creates.  So it should know about the VHDL file and where to find it.   

 

The problem seems to be on the other end with the Avalon Slave Translator component not being found.   In previous versions of Qsys, there was an actual component called "Avalon-MM Slave Translator" that could be used for this sort of thing, instead of using a custom VHDL file.   With v21.3 Platform Designer, that component does not show up in the list of available components.  I can see this component in the Quartus Pro install package in the ip/altera/merlin/altera_merlin_slave_translator folder, but it's not available in the list of components in Platform Designer.

 

I've tried several different IP search paths in Platform Designer, but all result in the same error message.

 

Thanks,

Terry

 

 

sstrell
Honored Contributor III
609 Views

The translator is used as part of the interconnect generated by PD, not something you usually have to add to a system design yourself.  Can you post your code, at least the top-level ports and your _hw.tcl file?

GLT1
New Contributor I
583 Views

Sure, 

 

The attached qar is slightly different than the original one I posted.  This version uses the component editor instead of the generic component (HDL) method.   Both methods result in the same error message.

 

The Qsys file is in the src folder (my_qsys.qsys).  Just open that in the Platform Designer and click "Generate" to reproduce the error.

 

Thanks,

Terry

ShengN_Intel
Employee
568 Views

I try to recreate the example design attached in platform designer.

I found out that if outputenable port under avalon_slave_0 is removed the errors disappear and HDL can be generated. The errors come out if outputenable port is added.

GLT1
New Contributor I
545 Views

Sheng,

 

I'll give that a try today and let you know how it goes.

 

Thanks,

Terry

RPYoshi
Beginner
391 Views

Thank you for the solution.

 

I ran into the same problem but my issue turned out to be a miss-label of a byteenable signal as writebyteenable.

Once this was fixed, the post transform connections were correct.

 

GLT1
New Contributor I
530 Views

Sheng,

 

I replaced the oe_n signal with a read signal and it now seems to be working OK.    Do you know if that is something that will be fixed in an upcoming version of Quartus Prime Pro?  

 

Thank you!

 

--

Terry

ShengN_Intel
Employee
520 Views

Hi Terry,

 

Don't have much idea yet. Need to wait for official finalized released notes or documents.

 

Thanks

Best regards,
Sheng

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