Quartus Prime and avalon mm bridge bit width meaning

[CAlex]

Hi,

Im so confused about each settings on width settings in quartus prime.

1. If Im not wrong, every address in QP is byte.

So 0x1 = 8bit instead of 1bit? Why?

2. In HPS, what is the meaning of the AXI bridge data width?

Like 128 bit means this bridge can transfer 128 bits/ pulse or 128 bits/s?

3. In Avalon MM bridge there are two param data width(default 32 bits) and symbol width(default 8 bits), what are those represent? If I have a IP with 32 bit buffer and a 1 bit signal it will put it into 2 32 bit long addresses?

4. If I have a 128 bit width AXI bridge connect to Avalon MM bridge then what is the two params' best settings?

5. If the slave is a on chip memory then what was its data width? Should that be the same as the Avalon MM pipeline bridge or AXI interface?

Thank you

Reguards.

[RichardTanSY_Intel]

I understand your confusion regarding the width settings in Quartus Prime. Allow me to address your questions:

1. In Quartus Prime, each address is typically represented as a byte. So, when you refer to 0x1, it would indeed be 8 bits (1 byte) instead of 1 bit. This is because the standard unit of storage and transfer in Quartus Prime is a byte.

2. In the context of the HPS (Hard Processor System), the AXI bridge data width refers to the width of the data bus used for transferring data between the HPS and the AXI bus. For example, if the bridge data width is set to 128 bits, it means that the bridge can transfer 128 bits of data per pulse or per transaction.

3. In the Avalon MM bridge, the "Data Width" parameter represents the width of the data bus used for transferring data between the Avalon MM bus and the IP core. "Symbol Width" is basically the size of your base unit of data - in this case it is in bytes so it would typically be 8-bit. 

4. You would need to consider the data width and symbol width of your Avalon MM bus and the AXI bridge to ensure compatibility and efficient data transfer. I do not have the answer for the best settings for these two parameters, you will need to set the necessary parameters for the bridges according to your design requirement.

You may checkout this how-to video on how to deal with AXI bridge and Avalon bridge. https://www.youtube.com/watch?v=LdD2B1x-5vo

5. If the slave is an on-chip memory, it can be the same as the Avalon MM pipeline bridge or the AXI interface, depending on how you configure the memory and the bus connections in your design. For further information, you may checkout the user guide here:

https://www.intel.com/content/www/us/en/docs/programmable/683130/23-1/size-82488.html

I hope this helps clarify most of your questions.

If you have any further questions, please feel free to ask.

Best Regards,

Richard Tan

p/s: If you find any answers from the community or Intel Support to be helpful, we encourage you to mark them as the best answer or rate them 4/5 in the survey. 

[RichardTanSY_Intel]

Dropping a note to ask if my last reply was helpful to you?

Do you need any further assistance from my side? 

Best Regards,

Richard Tan

[CAlex]

Hi,

Very detailed and clear answer, I will go through the resources first.

Please forgive me for the might be delayed reply.

Thank you

Reguards.

[CAlex]

Hi,

I now have a question.

If in FPGA side I have a avalon mm slave IP with 4 32-bit registers, the bridge is linked to the h2f Axi bridge,

so the first reg is addressed as  IP_bridge_addr (0xC000_0000 + ip offset) 

And in HPS I address the IP like:

uint32_t* reg_ip = (uint32_t*)  IP_bridge_addr.

with reg_ip + 1, it is pointed to the next reg or just forward 8 bits?

And how to write an IP with constant regs of each 32 bits wide, like all the Altera IPs and call it in HPS with pointer + x (x means the xth reg) .

Is that related to the ava bridge width and AXI bridge width?

Thank you

Reguards.

[RichardTanSY_Intel]

I apologize for the confusion. It appears that your follow-up question is specifically related to the HPS, which falls outside my area of expertise.

In order to receive accurate and helpful assistance, I recommend creating a new thread in the FPGA Embedded section of the forum. https://community.intel.com/t5/Intel-SoC-FPGA-Embedded/bd-p/soc-fpga-embedded-development-suite

I understand this may cause some inconvenience, and I genuinely apologize for that.

However, by starting a new discussion in the appropriate section, you'll have a better chance of receiving the assistance you need from experts in the field.

Thank you for your understanding.

Best Regards,

Richard Tan

[RichardTanSY_Intel]

Other than the question related to the HPS, do you need any further assistance from my side?

Best Regards,

Richard Tan 

[CAlex]

Yes,

1.if I set ava MM bridge to 32 data width and 8 symbol width, then each time the ava mm bridge will read 32 bit or 32*8 = 256 bit?

2.what is the use of symbol width?

3.if im transferring a 48 bit data from ip to hps through avalon mm bridge, will it transfer 2 32-bit long words?

Thank you.

[sstrell]

1) No, it's still a physical 32-bit bus so 32 bits.

2) Symbol width is for data organization.  With a 32 bit bus and a symbol width of 8 (the default), 4 symbols would be transferred per clock cycle.

3) If your bridge is set to 32 bits wide, then yes.

[CAlex]

Thank you for your answer, which is precise and clear.

Please have a good day

[RichardTanSY_Intel]

I'm glad to hear that your question has been addressed. Now, I will transition this thread to community support.

If you have any further questions or concerns, please don't hesitate to reach out.

Thank you and have a great day!

Best Regards,

Richard Tan