Quartus Prime issue

[KenCiszewski]

I'm learning Quartus Lite using the MAX II EPM240 CPLD.

I was able to compile successfully based on https://eecs.blog/max-ii-cpld-basic-getting-started-tutorial/,   a simple  counter/divider  design.

I was also able to compile successfully based on https://www.allaboutcircuits.com/projects/from-vhdl-code-to-real-hardware-designing-a-finite-state-machine/.

I'm waiting for hardware to test these.

In the meantime I decided that the counter could be used as a divider for the clock for the finite state machine, so I tried to create both of those in a single quartus file.  There were various difficulties, but I finally got something that might work, see the schematic picture attached.

The problem I ran into is that the pin planner wouldn't set a direction for the input (aclk) and output (out( on the counter, see the picture of the pin planner attached.

I tried to use the Assignment Editor, that didn't help.

Any thoughts?

[FvM]

Before assigning in- and outputs, the design schematic must be connected completely. Looks like counter is an empty box with no HDL code associated it, thus it doesn't show in- and outputs in pin planner.