Quartus Prime pro reported error during full Compilation

[RainGEHC]

My environment: Quartus Prime Pro 22.4, 10as016E4

Today I instantiated PLL in my design, then I clicked the “start compilation” button, then below error windows popped.

After I clicked the “cancel” button, the interface changed as below. You can see the fitter actually completed when the error occurred.

I also clicked the “review report” button and copied the error log as below FYI.

--------------------------------------------------

Problem Details
Error:
Internal Error: Sub-system: FDRGN, File: /quartus/fitter/fdrgn/fdrgn_expert.cpp, Line: 5653

Final postfit netlist check failed

Stack Trace:

  Quartus          0xe94f8: FDRGN_EXPERT::check_and_report + 0x568 (fitter_fdrgn)

  Quartus          0x21075: fit2_write_fitter_report + 0x1b5 (comp_fit2)

  Quartus          0x16442: TclNRRunCallbacks + 0x62 (tcl86)

  Quartus          0x17c4d: TclEvalEx + 0x9ed (tcl86)

  Quartus          0xa6a8b: Tcl_FSEvalFileEx + 0x22b (tcl86)

  Quartus          0xa5136: Tcl_EvalFile + 0x36 (tcl86)

  Quartus          0x22200: qexe_evaluate_tcl_script + 0x640 (comp_qexe)

  Quartus          0x20df2: qexe_do_tcl + 0x8c2 (comp_qexe)

  Quartus          0x29f51: qexe_run_tcl_option + 0x701 (comp_qexe)

  Quartus          0x29866: QCU::DETAIL::intialise_qhd_and_run_qexe + 0x116 (comp_qcu)

  Quartus          0x395ce: qcu_run_tcl_option + 0x76e (comp_qcu)

  Quartus          0x296c9: qexe_run + 0x5f9 (comp_qexe)

  Quartus          0x2aa0a: qexe_standard_main + 0x26a (comp_qexe)

  Quartus           0xbba2: qfit2_main + 0x82 (quartus_fit)

  Quartus          0x27998: msg_main_thread + 0x18 (CCL_MSG)

  Quartus          0x28952: msg_thread_wrapper + 0x82 (CCL_MSG)

  Quartus          0x2abd3: mem_thread_wrapper + 0x73 (ccl_mem)

  Quartus          0x24eb8: msg_exe_main + 0x178 (CCL_MSG)

  Quartus           0xcd2f: __scrt_common_main_seh + 0x10b (quartus_fit)

  Quartus          0x17613: BaseThreadInitThunk + 0x13 (KERNEL32)

  Quartus          0x526a0: RtlUserThreadStart + 0x20 (ntdll)

End-trace

Executable: quartus
Comment:
None

System Information
Platform: windows64
OS name: Windows 10
OS version: 10.0

Quartus Prime Information
Address bits: 64
Version: 22.4.0
Build: 94
Edition: Pro Edition

------------------------------------------------------------

After the error reported, if I try the timing analysis by “ctrl + shift + T”, the process can be started separately and completed successfully. And then I started the Assembler separately by clicking the “Processing->Start->Start Assembler”, this step can also be completed without error.

If  I deleted the PLL instance from my design, this error window will not appear after I click the “start compilation”, all steps will be completed.

I have checked this on several version as below, each version has the same phenomenon.

Quartus Prime Pro 20.1 windows

Quartus Prime Pro 20.1 linux

Quartus Prime Pro 22.3 linux

Quartus Prime Pro 22.4 windows

pls help to check this, thanks in advance.

[RichardTanSY_Intel]

I could not find this internal error in the database. Could you help to share your design .qar file (Project> Achieve Project) that could duplicate this error? With Quartus version 22.4.

We will need to duplicate the error as without the error duplication from our side, it would be hard to find a workaround/solution.

Best Regards,

Richard Tan

[RainGEHC]

yes, i can send you the qar file, pls provide me a private approach that i can send it to you.

i can not attach it here because of the business consideration.

thank you!

[RainGEHC]

hi, 

can i directly reply your support Email with the qar file attached? it is about 5M. I just tried the ftp but can't connect to it because of the corperation firewall.

thanks.

[RainGEHC · Accepted solution]

hi, Richard, 

I found this error is related to the pin assignment of the Lane 3 of bank 2K, which i have discussed via E-mail with you.

when I disable the EMIF, the pins can be driven normally. when I enable the EMIF, the pins can not be driven by logic. 

and i also found an Article with ID 000079165 from intel website, it mentioned that if HPS EMIF is enabled, Lane 3 of bank 2K can only be used as FPGA input only. I think this is the root cause.

if I delete the drive logic of these pins from my design, this IE will disappear. 

But the article also mentioned that the Quartus Prime software version 15.1.1 and earlier do not check for these restrictions, and the patch  for above restriction is also scheduled to be added to a future version of the Quartus Prime software.

But Quartus pro 22.4, what i am using, this version only report this IE which triggerd by this pin assignment restriction and doesn't report error as you showed to me.

[RichardTanSY_Intel]

I’m glad that your question has been addressed, I now transition this thread to community support. 

Thank you.

Best Regards,

Richard Tan

p/s: If any answer from the community or Intel Support are helpful, please feel free to give best answer or rate 4/5 survey.