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Chosing the mapping can be done with attributes in HDL - but this will only work if the logic is suitable. Why not post the code so we have some idea of whether it will work.
As a note though, Quartus will generally use Memory elements when it can, and only use LUTs if necessary. If it didnt default to RAM, there is probably an issue with the code.
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I'm novice at VHDL development. So, as I understand, the logic described in this way should use internal memory.
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.numeric_std.all;
entity ROM_ent is
port(
Q : in STD_LOGIC_VECTOR(5 downto 0);
Y2 : out STD_LOGIC_VECTOR(1 to 3)
);
TYPE Base IS ARRAY (50 DOWNTO 0) OF STD_LOGIC_VECTOR(1 TO 3);
constant ROM: Base := (
0 => "000",
1 => "110",
2 => "000",
3 => "011",
................
50 => "000");
end ROM_ent;
architecture ROM_ent of ROM_ent is
signal addr_u : unsigned(5 downto 0);
signal addr : natural range 0 to 50;
begin
addr_u <= unsigned(Q);
addr <= to_integer(addr_u);
Y2 <= ROM(addr);
end ROM_ent;
Also in the literature on the older versions of Quartus, I found references to the fact that it is possible to selectively select the type of logic on which the elements will be implemented.
