Quartus: Timing analysis

[Aswathi]

Hi Team,

I wrote a verilog code of an FSM in Moore model. Timing analyser identified one of the states as a clock. There are some combinational blocks , the input parameters of the combinational block are driven from the FSM. Why is an FSM state  being detected as clock? It should detect only the clock signal applied, ideally. How to do the reporting and timing closure in this case?

[sstrell]

Can you provide the HDL code for the state machine and your .sdc file?  It's hard to figure out what's going on without this info.

[SyafieqS]

Hi Aswathi,

More information needed here e.g sdc,fsm hdl snippet would be better