Quartus WE newbee - old logic designer

[Altera_Forum]

I'm tyring to start the transition from old logic design to CPLD's. I've been over the intro to quartus 2, etc. I'm trying to start simple and understand as I go. I'm at a point though of not sure it's not time to branch out of the schematic mode. Essentially what I want to do is to have a 5 bit up down counter and have been able to generate that via the wizzard (nice!), followed by a nibble rom to decode the 32 states down to 4 outputs. Rather than capture the logic graphically, is their another way other than learning VHDL?

[Altera_Forum]

That's kind of an ugly one in a schematic(as far as I can tell). The bottom line is VHDL has some nice advantages, but so does schematic. For right now, it's probably worth learning a little VHDL and just dropping that into your schematic. For example, you can create a New VHDL file, go to Edit -> Insert Template -> Vhdl -> Constructs -> Sequential -> Case Statement. Follow the syntax and put into a VHDL architecture(you'll also need an Entity, which is basically a description of the top-level ports). Then modify the case to do your encoding. When you're done, go to File -> Create Symbol for Current File. Then add it into your schematic. 

 The first pass will be difficult as you'll have some errors, as with any language, but it shouldn't be too bad. There are definitely arguments for going to VHDL, but if you're happy with schematic, stick with it and just have the comfort that you can use an HDL if and when you need to.

[Altera_Forum]

There is always verilog. 

You might find the overhead a little easier?  Everything above is good stuff. Enjoy the process.

[Altera_Forum]

I'm not enjoying the process. I'm having real difficulty in just creating a simple design in Quartus. I can create a create a project , block design file/block symbol file no problem. But I'm having difficulty understanding the realization of that to the device. I'm missing something that is probably really simple and I sure haven't dug it out of Altera's documents.....:confused: Or found a rudametary simple Quartus 2 example.

[Altera_Forum]

Ok figured out my compile problems. So the next question would be where can I look for direction on the "connection" between a VHDL text file and a graphic bdf file?

[Altera_Forum]

Well, I've been making this much harder than it actually was....:) Got some VHDL working with graphic block design files and running some timing simulation. Thanks. 

 Now the struggle is creating reasonable timing input files. :eek:

[Altera_Forum]

--- Quote Start ---  Now the struggle is creating reasonable timing input files.   --- Quote End ---    You should use ModelSim and a VHDL test bench which is the best way to test your design. If you are beginning with VHDL, you can get a training by Doulos. I had one a few year ago and it was really great. The instructor we had was a real expert and the training documents are very well made. In one week I learnt how to use VHDL. By yourself it will take ages and you will never be sure because many books and samples you find on the internet are full of bugs (for example about the sensitivity list).