I'm new with timing simulation and I have some difficulties with the implementation and I think it's because the timing, I don't want to go through the full story just to make it simple, so what I'm trying to do now run the gate level simulation, I'm using the latest quartus prime lite 17.1 lite edition and I wrote a code to implement it on de1-soc (cyclone V - 5CSEMA5F31C6), so after I compiled my code with the following setup:
1- in assignment/setting/EDA tools setting: simulation "modelsim-Altera" - verilog.
and nothing else here.
2- in tools/option: just copy the directory of the modelsim.
3- my top design module is not the test bench, it's the FSM for the code.
and that's it.
So, after I ran the RTL simulation, the functionality was correct, and now is the time for the gate level simulation, so after I did the EDA netlist writer I observe something missing, it's generate only <design>.vo, where I need both .vo and .sdo files.
My question is, why the software does not generate this file and how to generate it? because as far as I know I need this file for the timing simulation.
