I have an issue where as the Cyclone V fills up my design stops working. I took a look into what is happened and it seems that as the block memory fills up Quartus decides to share a ram block between a rom and as part of the logic for the 6502 CPU core I am using. This would be fine except when this sharing occurs the wrong results are returned and one of the instructions on the 6502 core thus does the wrong thing! I captured this in signal tap and have traces etc.
I've attached a .qar file with the design showing the issue.
I accidentally posted this question in the wrong forum before, there are more complete details here, along with signal tap traces and snippets form the technology map viewer.
I'm not sure if its a bug in my design or in Quartus. Usually these 'compiler bugs' turn out to be user error. However I'm really at a loss on this one. I've looked at it several times over the last year since discovering it and still have no idea how to resolve.