Quartus reports:can't pass value from actual to argument xxx.

[Altera_Forum]

Consider the following code: 

interface test_if# ( parameter BITW = 16 ); logic sigs; endinterface package test_pkg; function automatic int test_calc(int bitw); return bitw + 1; endfunction endpackage module test_mod# ( parameter BITW = 8 ) ( input bit clk, input wire rst); test_if# (.BITW(BITW)) tifi(); localparam int bitw_ofcalc = test_pkg::test_calc($size(tifi.sigs,1)); // on this line Quartus reports error message: can't pass value from actual to argument bitw initial $warning("DEBUG: bitw_ofcalc = %0d", bitw_ofcalc); endmodule   When synthesizing, quartus's integrated synthesizer report an error message just like the comments in code. I don't know what's wrong in code, could any one help me? Thanks very much!

[Altera_Forum]

Hello, 

 It also gives another error : Error (10192): Verilog HDL Defparam Statement error at analysis.sv(17): value for parameter "bitw_ofcalc" must be constant expression. And solution lies in this.  To solve this you can use : localparam int bitw_ofcalc = test_pkg::test_calc(BITW);  It would give you your expected result.  Thanks, Bhaumik

[Altera_Forum]

--- Quote Start ---  Hello,  It also gives another error : Error (10192): Verilog HDL Defparam Statement error at analysis.sv(17): value for parameter "bitw_ofcalc" must be constant expression. And solution lies in this.  To solve this you can use : localparam int bitw_ofcalc = test_pkg::test_calc(BITW);  It would give you your expected result.  Thanks, Bhaumik  --- Quote End ---    Thanks for replying! Well, In the example code the purpose of using '$size(tifi.sigs,1)' is to determine the vector's bitwidth automatically, for the interface 'test_if' has an instantiate-parameter named as 'BITW', it can be changed by user in coding. The next line of code is simulating the usage of instance in other code blocks or modules, the developer can not determine the bitwidth of that vector mannually without viewing the code of instance. I want synthesizer automatically determine the vector's bitwidth, in order to avoid some duplicated work of people, so the calling of '$size(tifi.sigs,1)' had better to be remained. I prefered to recognize this error as a bug of synthesizer, but I'm not sure whether there is no fault or mistake in my code, could you check them for me? thanks very much!

[Altera_Forum]

--- Quote Start ---  Hello,  It also gives another error : Error (10192): Verilog HDL Defparam Statement error at analysis.sv(17): value for parameter "bitw_ofcalc" must be constant expression. And solution lies in this.  To solve this you can use : localparam int bitw_ofcalc = test_pkg::test_calc(BITW);  It would give you your expected result.  Thanks, Bhaumik  --- Quote End ---    Thanks for replying. The line you suggest to change is just illustrating the using of another module. I want to determine the bitwidth of signal bus 'sigs' in interface through the interface instance, for the interface can be instantiated with various value on parameter 'BITW', and the module passed the instance as a port can only determine the signal's bitwidth by using system function '$size'. So I can't directly pass the parameter 'BITW' to function ‘test_pkg::test_calc'.  I had read the IEEE STD 1800-2012, and it seemed that there was no issue dissatisfy the constant function rule in chapter 13.4.3. I don't know whether there is some mistake or bug in the code above, could you help me check it?