I've a Custom controller design integrated with one instance of Arria10 Native FPGA transceiver. With this I could run synthesis & Implementation using Quartus tool successfully. We modified the design to include two instances of Arria10 Native FPGA transceiver. After this, the implementation run is taking long time (> 20hrs) and routing is not getting completed. I've attached a screen snapshot.
Is it design constraint related issue? Any suggestion to overcome this issue?