Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
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QuartusII Critical Warning:Ignored Power-Up Level option

Altera_Forum
Honored Contributor II
2,437 Views

Hi all, 

compiling my prject, I received this warning message: 

 

critical warning: ignored power-up level option on the following registers 

critical warning: register \freqcontrolloopprocess:nperiodcount[3] will power up to low 

critical warning: register \freqcontrolloopprocess:nperiodcount[2] will power up to low 

critical warning: register \freqcontrolloopprocess:nperiodcount[1] will power up to low 

critical warning: register \freqcontrolloopprocess:nperiodcount[0] will power up to low 

critical warning: register ndivisorh[3] will power up to high 

critical warning: register ndivisorl[3] will power up to high 

 

Where am I going wrong?
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5 Replies
Altera_Forum
Honored Contributor II
802 Views

Have you tried to power up some registers high, whilst resetting them to '0' with an async reset?

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Altera_Forum
Honored Contributor II
802 Views

Yes, in fact I set: 

 

ndivisorh : integer range 0 to max_cnt-1:=8; 

 

because reset value is: 

 

... 

if reset_i='1' then 

ndivisorh<=8; 

... 

 

 

the solution is to set the regs initially to the reset value they assume when reset='1' in the code.
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Altera_Forum
Honored Contributor II
802 Views

The warnings you posted dont refer to nDivisorH. They refer to nPeriodCount and nDivisorL

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Altera_Forum
Honored Contributor II
802 Views

even to nDivisorH 

 

 

--- quote start ---  

 

Critical Warning: Register nDivisorH[3] will power up to High[/B] 

 

 

--- Quote End ---  

[/B]
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Altera_Forum
Honored Contributor II
802 Views

Then I assume you've set an assignment that tells them all to power up low.

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