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Valued Contributor III
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QuartusII WebEd 7.1 does not infer shift register

Hello, 

 

I found a strange behavior of Quartus II WebEdition 7.1 (and Quartus 7.0). 

I build a shift register with VHDL, length e.g. 100, data width e.g. 60 Bits, see below. 

In Quartus II 5.1 this is (correctly) inferred as RAM. In Quartus 7.1 it is not. 

The settings are the same, except for Auto_Shift_Register_Replacement which changed from "ON" in 5.1 to "Auto" or "Always" in 7.1. 

Paradoxically Quartus 7.1 infers RAM when I reduce the shift-register length to 5!!! 

(in the code replace 100 by 5 and 99 by 4) 

 

I am confused. Can someone explain this? 

 

The VHDL code is as follows: 

(The Clock enabled seems to play a role.) 

 

ENTITY ShiftRegister IS 

PORT 

CLOCK : IN std_logic; 

RESET : IN std_logic; 

CLK_Enable : IN STD_LOGIC; 

DataIn : IN STD_LOGIC_VECTOR(60 DOWNTO 1); 

DataOut : OUT STD_LOGIC_VECTOR(60 DOWNTO 1) 

); 

END ShiftRegister; 

 

ARCHITECTURE behavior OF ShiftRegister IS 

 

TYPE type_Register IS ARRAY (INTEGER RANGE 1 TO 100) OF STD_LOGIC_VECTOR(60 DOWNTO 1); 

SIGNAL sig_Register : type_Register; 

 

BEGIN 

 

PROCESS (CLOCK, RESET) 

BEGIN 

IF RESET = '0' THEN 

ELSIF rising_edge(CLOCK) THEN 

IF CLK_Enable = '1' THEN 

sig_Register(2 TO 100) <= sig_Register(1 TO 99); 

sig_Register(1) <= DataIn; 

DataOut <= sig_Register(100); 

END IF; 

END IF; 

END PROCESS; 

 

END behavior; 

 

 

Greets 

Axel
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Valued Contributor III
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--- Quote Start ---  

Hello, 

 

PROCESS (CLOCK, RESET) 

BEGIN 

IF RESET = '0' THEN 

ELSIF rising_edge(CLOCK) THEN 

IF CLK_Enable = '1' THEN 

sig_Register(2 TO 100) <= sig_Register(1 TO 99); 

sig_Register(1) <= DataIn; 

DataOut <= sig_Register(100); 

END IF; 

END IF; 

END PROCESS; 

 

 

Axel 

--- Quote End ---  

 

 

The function you described in the VHdl lines is like a ram-------write your data and then read them out. I think the Quartus may sometimes read it as a ram or a shift_reg. 

The standard Quartus regards them as ram or shif_reg is a question in deed. 

I am looking forward to it ,too.
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Valued Contributor III
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I don't know if I understand what you mean. 

 

What I expect is: 

- Quartus regards the code as a shift register 

- automatically uses the megafunction "altshift_taps" and then uses RAM instead of LEs 

 

This is exactly what Quartus 5.1 does. 

Quartus 7.1 also uses RAM when there are less than around 10 elements in the shift register, but uses LEs if the shift register is longer. (I could understand if it were the other way round.)
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