Query Related to FMCA loopback

[Va3]

Hello,

I am trying to send the data from a counter to Native PHY IP and receiving back using the FMC Loopback Card.

The TX side data is transmitting correctly but the RX side I am receiving the wrong data. 

 I am using the Arria10_Devkit_4Ch_TTK example design and made the following changes:

https://community.intel.com/t5/FPGA-Wiki/High-Speed-Transceiver-Demo-Designs-Arria-10-Series/ta-p/735131

1. Reduced the PMA data width to 32. 

2. Number of channels to 1 with a data rate of 12.5 Gbps.

Also the clock configurations were : 

Counter is connected to 100 Mhz clk and PLL reference clk and rx_cdr clk is connected to 625 MHz ( REFCLK_FMCA_P).

BTW,  I am using Arria 10 GX Development Kit and Quartus Prime Pro Edition version 19.2.0.b57.

Thank you 

@intel 

[skbeh]

Hi Sir

The suggestion is you can try reduce the data rate to 11.3Gbps or lower.

According to Arria 10 Device Datasheet, Table 20. Transmitter and Receiver Data Rate Performance

If VCCR_GXB = VCCT_GXB = 0.95V, maximum data rate is 11.3Gbps.

Document link: https://cdrdv2.intel.com/v1/dl/getContent/683771

[Va3]

Hello,

When I checked after enabling the PRBS in my design. It is transferring data which I checked using the transceiver toolkit.

@intel 

Thank you

 

[Va3]

I am using Arria 10 GX Development Kit : https://www.intel.in/content/www/in/en/products/details/fpga/development-kits/arria/10-gx.html

And according to the schematics VCCR_GXB=VCCT_GXB=1.03V 

Thank you

[skbeh]

Hi Sir

A suggestion would be use a simpler design to verify first then only start to take it from there.

You can download A10 NativePHY with transceiver toolkit design example at below link, targeting Arria 10 dev kit too.

https://community.intel.com/t5/FPGA-Wiki/Arria10-Transceiver-PHY-Basic-Design-Examples/ta-p/735196

This is a simple 1.25G 1 channel design with ATX PLL. You can use transceiver toolkit to perform “serial loopback” as starting point.