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14968 Discussions

Questa/Modelsim, long SV variable in object

KVino1
Beginner
844 Views

 

Hi,

I have the same problem on Intel free Modelsim and both in Commercial Questasim CADs.

 

Here's my SystemVerilog signals, I want to check in simulator

logic [8191-1:0] ram_buffer0 ; logic [8192-1:0] ram_buffer1 ; logic [4000-1:0][2-1:0] ram_buffer2 ;

The problem is that there's no ram_buffer1 variable in objects list pallete in saved WLF file. I can't add to waveform both manually and through command

# (vish-4014) No objects found matching 'vsim:/row_buffering_tb/UUT/ram_buffer1'.

This problem happens when variable size more then 8191 elements.

My shell scripts is also quite simple

vdel -lib work -all   vlib work     vmap work $PWD/work rtl=../rtl tb=../tb   verlist=( $rtl/row_buffering.sv $tb/row_buffering_tb.sv )   for src in "${verlist[@]}" do vlog -sv $src done   vsim -t ps -novopt work.row_buffering_tb -do "log -r /*; run 2 us; exit;"

The problem is with saving signal into WLF - I can do something like

 

logic [10000-1:0][5:0] test_ram_buffer_long ; logic [5:0] test_ram_buffer_last ; assign test_ram_buffer_long[10] = 42; assign test_ram_buffer_last = test_ram_buffer_long[10];

There will be now in test_ram_buffer_long in object list, but assignment of test_ram_buffer_last will works fine.

 

The problem doesn't depend on packed/unpacked array declaration type

 

0 Kudos
2 Replies
Vicky1
Employee
77 Views

Hi,

Can you share the project file or row_buffering_tb.sv file, if possible?

 

Best Regards

Vikas Jathar 

(This message was posted on behalf of Intel Corporation)

 

Abe
Valued Contributor II
77 Views

I just tried the same with a simple RAM model and I'm able to view all the mem_buffs in the object browser. Take a look at the screenshot

 

mem_code.JPG

 

Same with mem_buff3 size 4096x20

 

mem_code1.JPG

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