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Questa Simulation Not Showing All Needed Variables

VHDL_User
Beginner
609 Views

I am using Quartus to write my program in and am trying to simulate this in Questa. My program compiles in both applications. When I begin simulation in Questa, some inputs and outputs are missing. They do not appear in the Objects tab where I would be able to pull them over to the simulation tab. Does anyone know where I can find these missing variables to view in simulation? I am using Quartus Prime Pro version 21.3.

0 Kudos
13 Replies
mistersinha
Beginner
589 Views

same query

SyafieqS
Moderator
582 Views

Miceli,


Is possible to provide sample design and steps that replicate the issue? this could be a bug for Questa since it is recent adopt to Quartus.




SyafieqS
Moderator
537 Views

Miceli,


May I know if there is any update from my previous query?


VHDL_User
Beginner
534 Views

It ended up being a setting that was automatically turned on for Questa but not for Modelsim. It took me awhile to find because I had never had to change the setting in the past. When simulation is started, there's and optimization setting that must be switched to show full visibility to all variables. 

DrNickels
New Contributor I
169 Views

Could you share what this setting was and how to change it for those coming after with the same problem?

SyafieqS
Moderator
529 Views

Miceli,


Noted. Seem the issue was resolved let me know if there is any other query at your end otherwise Ill put this to close pending.


KCMurphy
New Contributor II
152 Views

The issue here is "optimization" which needs to be turned off for logic debug, and probably always in an FPGA design.  For verilog, right click on a source, choose "compile properties" and check "use vopt flow"  and maybe you want to select an optimization level under coverage.  I believe that these settings are project wide.  If you need to look into an Altera IP block, you may have to put a comile option into the msim_setup.tcl file.  Haven't tied that.

 

Note:  I solved this about a year ago and may be a bit fuzzy on the path.

 

 

DrNickels
New Contributor I
146 Views

Thanks, that gives me a direction to go.  I'm using VHDL. 

In Questa, I went to "Compile Options" and "Use vopt flow" was already selected.  I tried unselecting it (and recompiling and reloading my testbench) with no change.  I also tried selecting "Disable optimizations by using -O0" with the same result.

KCMurphy
New Contributor II
143 Views

Look in the manuals for the vhdl compile command line.  In verilog you want the -vopt flag. 

DrNickels
New Contributor I
132 Views

I can't find the "Fine Manual" to read :). 

The Help/Questa PDF Bookcase is all dead links.  Nothing online seems to have current versions (21.1).  vcom does have a -vopt flag, but it doesn't seem to expose variables.

KCMurphy
New Contributor II
126 Views

It should be in your installation directory

 

C:\intelFPGA_pro\21.3\questa_fe\docs\pdfdocs\

 

If you don't have the Intel version, you can download it and get the PDFs

DrNickels
New Contributor I
112 Views

Ok, I found the QuestaSim manuals.  Looks like I'd need to dig into the scripts that Quartus Prime uses to call Questa Intel FPGA Edition to make that happen.  That's pretty ugly.  And it seems like calling with -O0 (which is a menu option in Questa and generates a warning about slowness of simulation so I know it's being read) would do this.

 

Update: in Questa Intel FPGA Edition, you go to Compile/Compile Options, then select the Coverage Tab under "Other Coverage" (the 4th box in 21.1), is an option "Enable Finish State Machine Coverage (+cover f)".  If you select that, then hop out of questa and back to quartus and restart questa - yes I'm sure there is a quicker way to do that - then the process in https://nandland.com/view-variables-in-modelsim-waveform/ works - the state, which is a variable, shows up.

 

Thanks for the help.

KCMurphy
New Contributor II
107 Views

It's probably a good thing to read msim_setup.tcl and create your own startup call into that, using ld_debug and enum_debug as shown in the verbose output from the setup tcl.  But I wouldn't go so far as to modify them directly as they can get recreated by Quartus.

 

Here's my normal startup:

do ../mentor/msim_setup.tcl
set TOP_LEVEL_NAME testbench_test
set FORCE_MODELSIM_AE_SELECTION true
set SILENCE true
elab_debug -suppress 3016 -t 1ps
do wave.do

 

and my rebuild when I create a new IP module in quartus and generate a new script for msim.

 

do ../mentor/msim_setup.tcl
set TOP_LEVEL_NAME testbench_test
set FORCE_MODELSIM_AE_SELECTION true
set SILENCE true
ld_debug -suppress 3016 -t 1ps

 

 

 

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