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I am encountering a crash when running a small testbench on Questa-Intel FPGA Starter Edition (versions 2022.1 and 2021.1), as follows:
...
# vcd file wave.vcd
# vcd add -r *
# Attempting stack trace sig 11
# Signal caught: signo [11]
# vsim_stacktrace.vstf written
# Current time Tue Sep 27 09:49:24 2022
# Program = vsim
# Id = "2022.1"
# Version = "2022.01"
# Date = "Jan 29 2022"
# Platform = win64
# Signature = 99b83b9327725e31dac8178b441b88b1
# End of Stack Trace
** Fatal: (SIGSEGV) Bad pointer access. Closing vsimk.
** Fatal: vsimk is exiting with code 211.
Exit codes are defined in the "Error and Warning Messages"
appendix of the QuestaSim User's Manual.
# End time: 09:49:24 on Sep 27,2022, Elapsed time: 0:00:01
# Errors: 0, Warnings: 0
The source and instructions in the attached ZIP demonstrate the issue.
Link Copied
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Hi Adam,
I tried to run the simulation using Quartus flow (nativelink) and seem there is synthesis issue as below
Error(19750): VHDL error at ps2_host.vhd(53): formal generic fclk has no actual or default value
Assuming you are running the design independently with Quartus and Questa, maybe you can try to use nativelink method and see if thats possible.
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Hi @SyafieqS
ps2_host is an IP core intended to be instantiated rather than used as the top level - but you can work around this by setting the generic value as follows in Quartus: Assignments - Settings - Compiler Settings - Default Parameters; then create and add a parameter named fclk with a value of 1.0.
I tried simulating via NativeLink, and entered my vsim command at the Questa command prompt. The tool then crashed and exited without displaying an error message.
-Adam
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Adam,
Thanks for that. Let me reproduce the issue and investigate this. Will let you know if there is any update
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Hi Adam,
Since this case been idling quite sometime, may I know if you still need any help on this?
Did you manage to solve it?
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Hi Adam.
Questa will sometimes crash and disappear when it encounters confusing situations. Try running it all by itself, without calling it from another app. Try loading a simple, totally different HDL project to see if the problem changes.
The symptom you describe, disappearing when you add signals to the wave window, is very common with an incorrect license.
I have not able to replicate the issue due to bandwidth circumstances but here few ways I could think of
1. If you're sure that your lic file is ok, try to place it in a new folder. Call it for example msim.dat in toto folder.
In the environment variables, add the new environment.
example: LM_LICENSE_FILE set to c:\flexlm\license.dat
change it to
c:\toto\msim.dat;c:\flexlm\license.dat
In turn your Questa FSE license will be read first
2. Deleted all files in the Questa FSE project folder, except for the source files and re-compiled
Let me know if this is working
p/s: If any answer from community or Intel support are helpful, please feel free to mark as solution, give Kudos and rate 10/10 survey
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As we do not receive any response from you on the previous question/reply/answer that we have provided. Please login to ‘https://supporttickets.intel.com’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.
p/s: If any answer from community or Intel support are helpful, please feel free to mark as solution, give Kudos and rate 10/10 survey
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@SyafieqS I was not notified when you replied.
The issue is not licensing. Questa works fine with many other designs. I can add waves to a VCD in other designs without a problem. Deleting intermediate files and recompiling is not helping.
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