Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
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Questa intel FPGA has no delay to Gate level simulation

hokagechichi
Beginner
878 Views

I used Cyclone IV (EP4CE6E22C8), and the delay should be 9ns. However, my Gate level simulation's delay was 0. What should I do?

 

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sstrell
Honored Contributor III
849 Views

It doesn't look like you are running a gate-level sim.  It looks like a standard RTL sim.

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SyafieqS
Employee
839 Views

That seem to be rtl simulation. And also, it is always better to use sta for timing instead gate level for timing.


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SyafieqS
Employee
796 Views

Let me know if there is any update


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hokagechichi
Beginner
787 Views
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AEsqu
Novice
773 Views

Maybe you need to synthesize the RTL first?

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FvM
Valued Contributor III
769 Views

I'm missing the step where you import the gate level netlist.

hokagechichi
Beginner
728 Views

Finally, I found that I should turn off "Generate functional simulation netlist", then the gate level simulation will display correctly.

ref:  https://www.youtube.com/watch?v=HFWd7QPibMY&t=400sh

 

Thank to everyone.

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SyafieqS
Employee
687 Views

I’m glad that your question has been addressed, I now transition this thread to community support. If you have a new question, Please login to ‘https://supporttickets.intel.com/’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.


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