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I run a Questa simulation for an IP core from the command line on a Linux server. Usually, the simulation finishs successfully. But every now and then the simulation hangs.
When it hangs, I can see that the CPU load is 100% but I can't break the simulation by hitting Ctrl-C. The key-press is detected ("# Break key hit") but the simulation won't halt.
Since I use the same seed for random number generation in each run, this seems like nondeterministic behavior.
I have no clue, where this behavior is comming from. Are there any command line options that I can use to get closer to the problem? How can I go one with debugging in such a case?
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I'm now trying to create a Quartus project to run the simulation.
Analysis and synthesis works fine. But it seems that Quartus does not respect the correct compile order for the files when generating the Questa "*_run_msim_rtl_vhdl.do" script. The script tries to compile the architecture of a module before its entity which results in a compiler error.
(I moved the entity compilation call manually before the architecture compilation and it worked then.)
The file order in the QSF file is correct and the same as in "Settings -> Files". How can I force Quartus to keep this order when generating the Questa DO script?
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Sorry for the delayed response, can you help share the script and specify the lines causing the error. Thanks.
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Hi there, is there any updates
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Hi,
sorry for the late reply, I've been on vacation for 2 weeks.
I attached the generated script to this post. The error is caused by line 14:
# ** Error: (vcom-11) Could not find work.th_dnx_simpledualportram.
"th_dnx_simpledualportram_bhv_a.vhd" contains the architecture definition of th_dnx_simpledualportram.
However, the entity definition is in "th_dnx_simpledualportram_e.vhd", which is compiled in line 17.
I think, this is the wrong compile order.
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Hi there, thanks for the information. Could you please help specify what steps you do when generating the script.
BTW, you may try to change the files order in the 'setting - files'. Try to move this file to the top of the list to see if it helps.
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First, I do "Analysis & Synthesis" for the project. Then I go to "Tools -> Run Simulation Tool -> RTL Simulation". Then Questa comes up and fails while compiling the sources.
The file order in "Settings -> Files" is correct. The file order in the script is different than what I see in "Settings -> Files".
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I see. Could you help provide the project for reproducing the issue? Let me check whether it's a software issue.
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I've sent you a mail with a link to our file exchange server. Please download the project from there.
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Hi there, I have tried to reproduce the issue with the file you provided but failed in the first step and shows the follow message:
Error (12007): Top-level design entity "shipment" is undefined
Seems that some files are missing.
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I fixed an issue with the revision name that caused the 12007 error. It should work now. I've sent you a mail with a link to our file exchange server. Please download the project from there.
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ohh, I get it
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Hi thaler, Sorry for the delayed response as I just back from leaving. The shared link has expired. Could you please share it again.
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Hi Thaler, I tried to modify the file as what you showed, but it caused error during simulation as follow:
** Error: (vcom-11) Could not find work.th_dnx_genericram.
Can you share the '.do' file works in your side, thanks
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I was able to fix the do file. Now the simulation can be run. Please find attached the do file.
Unfortunately Quartus generates absolute paths in it. But if you compare your and my do-file you should be able to do the same changes to yours.
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I tried your updated example, and it works well. Thanks a lot for your sharing.
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Hi TingJiangT,
Any progress on this? Were you able to reproduce the hangups?
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It seems like this case has been closed by support. However, I'm still looking for a solution for this issue.

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