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AEsqu
Novice
1,477 Views

REMOVE_REDUNDANT_LOGIC_CELLS is important, take care.

Hi,

Pay attention to leave the REMOVE_REDUNDANT_LOGIC_CELLS option to ON if you are using a reconfig pll [at least in stratix 3 FPGA].

Turning the option OFF makes 3 redundant cells not removed and the PLL fails to produce aproper clock after reconfiguration.

File is altpll_reconfig_quartus.vhd,

SIGNAL cuda_combout_wire : STD_LOGIC_VECTOR (3 DOWNTO 0);

 

--Quartus VERSION 13.1

0 Kudos
8 Replies
KennyT_Intel
Moderator
20 Views

Hi,

 

Can you circle out the different base on your screenshot?

 

I will try it on Q18.1 to see if the problem still exist.

 

Thanks,

AEsqu
Novice
20 Views

Hi,

Please see the diff in the new attachment.

pll_reconfig_diff.png

AEsqu
Novice
20 Views

Please note that timings are meet for setup and hold in both scenario's,

so this is not timing related (slack of +0.3 ns).

 

If you need the qar to reproduce it, let me know (give me your personal placeholder as I cannot give it on the forum).

 

Please note that I will stick to v13.1 (last supported version for the stratix III fpga).

 

KennyT_Intel
Moderator
20 Views

Hi,

 

I had send you a separate mail for the qar. you may check your inbox

 

Thanks,

Best regards,​

AEsqu
Novice
20 Views

So, what is the outcome KTan9?

Is the issue still present?

KennyT_Intel
Moderator
20 Views

Hi,

 

Sorry, I had been quite busy. I will test it by today.

 

Thanks

KennyT_Intel
Moderator
20 Views

Hi,

 

Given that this bugs is in the older version of Quartus Prime, this bug/issue is currently in the lower priority list for Intel to fix. We apologize for any inconvenience. 

 

Thanks

AEsqu
Novice
20 Views

I removed manually in the RTL code the lines cuda_combout_wire as sometime quartus was still not removing them for some reason.

Now it works fine.

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