Pay attention to leave the REMOVE_REDUNDANT_LOGIC_CELLS option to ON if you are using a reconfig pll [at least in stratix 3 FPGA].
Turning the option OFF makes 3 redundant cells not removed and the PLL fails to produce aproper clock after reconfiguration.
File is altpll_reconfig_quartus.vhd,
SIGNAL cuda_combout_wire : STD_LOGIC_VECTOR (3 DOWNTO 0);
--Quartus VERSION 13.1
Please note that timings are meet for setup and hold in both scenario's,
so this is not timing related (slack of +0.3 ns).
If you need the qar to reproduce it, let me know (give me your personal placeholder as I cannot give it on the forum).
Please note that I will stick to v13.1 (last supported version for the stratix III fpga).
Given that this bugs is in the older version of Quartus Prime, this bug/issue is currently in the lower priority list for Intel to fix. We apologize for any inconvenience.