I add a simple pll to my design and i continue to run into the following error even though i don't have that port.
Error: RST_N port on the PLL is not properly connected on instance SOC_27Mhz_clk|iopll_0|altera_iopll_i|twentynm_pll|iopll_inst. The reset port on the PLL must be connected. If the PLL loses lock for any reason, you might need to manually reset the PLL in order to re-establish lock to the reference clock.
Info: Must be connected
below is my pll equations:
.rst (syn_reset), // reset.reset
.refclk (clk_50mhz), // refclk.clk
.locked (socpll_locked), // locked.export
.outclk_0 (clk27mhz) // outclk0.clk
any idea how to deal with this? I am using Quartus 18.1 pro