I am working on Quartus Pro 18.1 with an Arria 10.
In the design I need to use, as a tranceiver, a LVDS SERDES IP for 18 channels in the Bank 3A.
The problem I have is in regard of the Reference Clock of the I/O PLL that I want to use with the LVDS (the PLL being internal or external to the LVDS). All the Clocks I have specified as a Reference Clock give me an error: it is not a dedicated Clock from the corresponding Bank.
The only solution i have found is to use the actual dedicated clock pins of the Bank.
The problem i have with that is that, then, I would need an External Clock connected to those pins ? Is there a way to use an already existing Clock from the board or the output of an other PLL in the design as the reference clock for this PLL ?
Thank you in advance for your answer,
The issue with not using a dedicated input clock is that your generated clock's jitter can end up being terrible. Is this a custom board you are designing or an off-the-shelf solution?
Sorry for the delay !
To answer AndyN question it is an off-the-shelf solution that I am designing.
The problem that I have is that a PCB has already been done for the pins with the dedicated clock pins of the Bank3A as outputs of the LVDS SERDES (thinking that it was possible to use any clock of the board as the reference clock for the PLL feeding the LVDS SERDES). I wanted to be sure that it is required to modify the PCB.
I have tried, with different clock linked to the reference clock of my PLL, to set the assignment as you said. However I keep having the same Fitter error regardless of the assignment:
"The reference clock on PLL "..|..|internal_pll.pll_inst|altera_lvds_core20_iopll", which feeds an Altera LVDS SERDES IP instance, is not driven by a dedicated reference clock pin from the same bank. Use a dedicated reference clock pin to guarantee meeting the LVDS SERDES IP max data rate specification."
By using the reference clock pin I have completed the compilation, so it seems that it is mandatory to do so but I didn't find in the documentation where it is mentionned that it is. Because for the I/O PLL the documentation specifies that the reference clock could be GCLK or RCLK for instance, but it seems that if it used for the LVDS SERDES only the dedicated clock pins are accepted ? And so, why this constrain ? To avoid a terrible jitter as you said ?
Also, it is possible to use an external PLL to feed the LVDS SERDES. But for me it is basically the same PLL as the one it creates internally with the LVDS SERDES IP. Do you have any clarification on what the external PLL is or what it means ?
Thank you in advance for your answer.
Sorry , I didnt notice your reply ..
Answer to your question,, Yes It is to reduce the jitter error , Quartus tool is intelligent enough to calculate take the preventive measure during fitter.
About the external PLL , yes you are correct .It will instantiate the same PLL as one it creates internally.but only difference is you can constraint the PLL in qsf based on your design.
Kindly let me know if you have any questions /concern ?
Thank you ,