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Valued Contributor III
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Relationship between Instantiating, Wires, Registers

My top module has 3 signals 

(clk,rst : Inputs 

Display : output) 

I'm trying to instantiate another module which also has the same 3 signals. 

In my top module i used display as a "reg" for calculation purposes. 

When i try to instantiate i get an error saying " output or inout port display must be connected to a structural net. 

So i changed Display to a net.  

Now i get an error saying "left hand side must be of variable data type" 

I also tries using a temporary variable to circumvent this problem but keep getting the same error  

"left hand side must be of variable data type" 

What do i do..?
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Valued Contributor III
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Valued Contributor III
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Thank you. 

That was informative
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