Request of feedback on SPI Slave moduel

[Altera_Forum]

Hello 

 I'm new on the hardware design world so probably I'm making a some beginner mistake.  I need to write a SPI Slave module, my first attempt was to make a SPI slave module using as reference the main clock(in this case 25MHz) and it in most of the time, I have 1% of error with any (1MHz or 4MHz of sclk the clock frequency don't change the error rate) So I decided that was time to write a implementation that use sclk as reference.  http://pastebin.com/ddfxsuck  But this one don't work at all on my MAX10, causing wrong values being read and write from SPI. On the other side using Icarus Verilog simulator it works.  It only supports SPI mode 0.  Some warnings that I got when synthesizing with Quartus that maybe could help, but I can't find how to fix then.  http://pastebin.com/pyptcxmd  Thanks

[Altera_Forum]

I notice you're using the sclk to clock the logic - the usual way of working is to use a system clock (clk in your case) that is many times the frequency of sclk, and treat sclk as any other signal and sample it. Then you generate "rise" or "fall" pulses to enable the registers in your design that all run at the system clock frequency.

[Altera_Forum]

--- Quote Start ---  I notice you're using the sclk to clock the logic - the usual way of working is to use a system clock (clk in your case) that is many times the frequency of sclk, and treat sclk as any other signal and sample it. Then you generate "rise" or "fall" pulses to enable the registers in your design that all run at the system clock frequency.  --- Quote End ---    Yeah that was my first implementation: http://pastebin.com/r7y7u7tx But I have 1% of error with this implementation. My main clock(25MHz) is not much faster than SCLK(4MHz if possible I want to work at 10MHz) maybe that is why I can not have the implementation based on main clock.  But still I can not understand why the implementation based on SCLK do not work at all any ideas?