Resource usage increase Quartus Lite 2020.1 vs 2019.1

[dsmr]

Hi,

I have a design which is unchanged since years, and the update to a new Quartus version was normally painless - rerun the synthesis script, that's it.  However with Quartus 2020.1 it suddenly does not fit anymore. The map.rpt files (see below) show a massive increase in resource usage, but slightly reduced memory. Possibly, some memory has been converted to logic.

I tried area optimization and also several of the detailed synthesis options, but no success. Any idea how to get the old behavior back?

Thanks,

Dirk

+----------------------------------------------------------------------------------+
; Analysis & Synthesis Summary                                                     ;
+------------------------------------+---------------------------------------------+
; Analysis & Synthesis Status        ; Successful - Sun Jan  3 19:32:53 2021       ;
; Quartus Prime Version              ; 20.1.1 Build 720 11/11/2020 SJ Lite Edition ;
; Revision Name                      ; vrfX                                        ;
; Top-level Entity Name              ; vrfX                                        ;
; Family                             ; Cyclone IV E                                ;
; Total logic elements               ; 141,594                                     ;
;     Total combinational functions  ; 96,628                                      ;
;     Dedicated logic registers      ; 68,622                                      ;
; Total registers                    ; 68622                                       ;
; Total pins                         ; 8                                           ;
; Total virtual pins                 ; 0                                           ;
; Total memory bits                  ; 2,063,670                                   ;
; Embedded Multiplier 9-bit elements ; 300                                         ;
; Total PLLs                         ; 1                                           ;
+------------------------------------+---------------------------------------------+


+----------------------------------------------------------------------------------+
; Analysis & Synthesis Summary                                                     ;
+------------------------------------+---------------------------------------------+
; Analysis & Synthesis Status        ; Successful - Sun Jan  3 19:06:12 2021       ;
; Quartus Prime Version              ; 19.1.0 Build 670 09/22/2019 SJ Lite Edition ;
; Revision Name                      ; vrfX                                        ;
; Top-level Entity Name              ; vrfX                                        ;
; Family                             ; Cyclone IV E                                ;
; Total logic elements               ; 87,847                                      ;
;     Total combinational functions  ; 74,929                                      ;
;     Dedicated logic registers      ; 36,574                                      ;
; Total registers                    ; 36574                                       ;
; Total pins                         ; 8                                           ;
; Total virtual pins                 ; 0                                           ;
; Total memory bits                  ; 2,096,438                                   ;
; Embedded Multiplier 9-bit elements ; 300                                         ;
; Total PLLs                         ; 1                                           ;
+------------------------------------+---------------------------------------------+

[SyafieqS]

Hi Dirk,

Could you provide the qar of your design if possible to replicate? Can send it via private message if it confidential.

[dsmr]

Hi,

meanwhile I found the problem. About 15 years ago, I modeled a simple RAM after an Altera-Megafunction using registered inputs. I remember finding this a bit weird, but that way Quartus managed to infer RAM instead of logic - at least until 2019.

It seems as of 2020 Quartus refuses to infer RAM for the code below.  Is there any way to get the old behavior back? I have tried changing the RAM model to use registered outputs, but that changes the behavior in some rare cases.

Kind regards

Dirk

module spRam1(q, d, adr, we, clk);

// define parameters
parameter m = 10;    // Address width
parameter n = 1024;  // Number of elements
parameter w = 8;     // Data width

// define inputs and outputs
output [w-1:0] q;    // Data output
input  [w-1:0] d;    // Data input
input  [m-1:0] adr;  // Read/write address
input          we;   // Write enable
input          clk;  // Clock

// define internal states
reg [w-1:0] mem[n-1:0];  // Memory
reg         weD;         // Delayed read enable
reg [m-1:0] adrD;        // Delayed address
reg [w-1:0] dD;          // Delayed data

// synchronous memory operation - input is registered (as in Altera Megafunction)
always @(posedge clk) begin
  weD  <= we;
  adrD <= adr;
  dD   <= d;
  if (weD)
    mem[adrD] <= dD;
end

// assign output
assign q = mem[adrD]; // Output if read enable in
                      // the previous cycle
endmodule

[sstrell]

The Quartus template for an inferred RAM is:

	always @ (posedge clk)
	begin
		if (we)
			ram[addr] = data;

		// Read returns OLD data.	To return
		// NEW data, use = (blocking write) rather than <= (non-blocking write)
		// in the write assignment.	 NOTE: NEW data requires extra bypass
		// logic around the RAM on Stratix10.
		q <= ram[addr];
    end

I'm not sure what behavior change you are referring to, but the read side of the RAM should be in the same process.  It's been like this for as long as I can remember.

[SyafieqS]

Hi Dirk,

You can refer below doc related to Inferring RAM using coding styles. 

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug-qps-design-recommendations.pdf - Design Recommendations (pg45)