Reversing a bus in SystemVerilog

[AWilc1]

Is there a way to reverse a bus in systemverilog?

I am trying to do:

genvar j;

generate

  for ( j=0 ; j < 256 ; j=j+1 ) begin

    out[j] <= in[256-j];

  end

endgenerate

But when I compile in ModelSim I get the errors:

** Error: (vlog-13069) near "[": syntax error, unexpected '['.

** Error: (vlog-13205) Syntax error found in the scope following 'out'. Is there a missing '::'?

I cannot see what is wrong here. Can anyone more familiar with SV see what is wrong?

Thanks.

[dave_59 · Accepted solution]

The problem is with the procedural assignment statement inside your generate loop. Assuming out is declared as a wire, you need to change it to

for (genvar j=0j<256;j++) assign out[j] = in[256-j];

But there us a much simpler way of writing this without a loop using the streaming operator

assign out = {<<{in}};