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Run Functional Simulation Error

Altera_Forum
Honored Contributor II
‎12-26-2017 06:58 PM
4,231 Views

I've just installed the QUARTUS II, and i am trying to run a simulation because i'm receiving the message below, can i have help solving this please? thanks

 

Device family: MAX7000S

Running quartus eda_testbench

>> quartus_eda --gen_testbench --check_outputs=on --tool=modelsim_oem --format=verilog test -c test {--vector_source=C:/Users/tracy/Documents/test/Waveform.vwf} {--testbench_file=./simulation/qsim/test.vt}

PID = 8580

************************************************** *****************

Running Quartus II 64-Bit EDA Netlist Writer

Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version

Processing started: Tue Dec 26 18:51:19 2017

Command: quartus_eda --gen_testbench --check_outputs=on --tool=modelsim_oem --format=verilog test -c test --vector_source=C:/Users/tracy/Documents/test/Waveform.vwf --testbench_file=./simulation/qsim/test.vt

Generated Verilog Test Bench File ./simulation/qsim/test.vt for simulation

Quartus II 64-Bit EDA Netlist Writer was successful. 0 errors, 0 warnings

Peak virtual memory: 375 megabytes

Processing ended: Tue Dec 26 18:51:21 2017

Elapsed time: 00:00:02

Total CPU time (on all processors): 00:00:02

Running quartus eda_func_netlist

>> quartus_eda --functional=on --simulation --tool=modelsim_oem --format=verilog test -c test 

PID = 14608

************************************************** *****************

Running Quartus II 64-Bit EDA Netlist Writer

Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version

Processing started: Tue Dec 26 18:51:22 2017

Command: quartus_eda --functional=on --simulation=on --tool=modelsim_oem --format=verilog test -c test

Generated file test.vo in folder "C:/Users/tracy/Documents/test/simulation/modelsim/" for EDA simulation tool

Quartus II 64-Bit EDA Netlist Writer was successful. 0 errors, 0 warnings

Peak virtual memory: 375 megabytes

Processing ended: Tue Dec 26 18:51:23 2017

Elapsed time: 00:00:01

Total CPU time (on all processors): 00:00:02

************************************************** *****************

Running quartus modelsim

>> vsim -c -do test.do

PID = 9300

Reading C:/altera/13.0sp1/modelsim_ase/tcl/vsim/pref.tcl 

 

# 10.1d

 

# do test.do 

# ** Warning: (vlib-34) Library already exists at "work".

# 

# Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov 2 2012

# -- Compiling module test

# 

# Top level modules:

# test

# Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov 2 2012

# -- Compiling module test_vlg_sample_tst

# -- Compiling module test_vlg_check_tst

# -- Compiling module test_vlg_vec_tst

# 

# Top level modules:

# test_vlg_vec_tst

# vsim -L max7000s_ver -L altera_ver -L altera_mf_ver -L 220model_ver -L sgate -c -t 1ps -novopt work.test_vlg_vec_tst 

# Loading work.test_vlg_vec_tst

# ** Error: (vsim-19) Failed to access library '/../altera/verilog/max' at "/../altera/verilog/max".

# 

# No such file or directory. (errno = ENOENT)

# Loading work.test

# ** Error: (vsim-19) Failed to access library '/../altera/verilog/max' at "/../altera/verilog/max".

# 

# No such file or directory. (errno = ENOENT)

# ** Error: (vsim-3033) test.vo(71): Instantiation of 'max_io' failed. The design unit was not found.

# 

# Region: /test_vlg_vec_tst/i1

# Searched libraries:

# ** Error: (vsim-19) Failed to access library '/../altera/verilog/max' at "/../altera/verilog/max".

# 

# No such file or directory. (errno = ENOENT)

# c:/altera/13.0sp1/modelsim_ase/altera/verilog/altera

# c:/altera/13.0sp1/modelsim_ase/altera/verilog/altera_mf

# c:/altera/13.0sp1/modelsim_ase/altera/verilog/220model

# c:/altera/13.0sp1/modelsim_ase/altera/vhdl/sgate

# C:/Users/tracy/Documents/test/simulation/qsim/work

# ** Error: (vsim-19) Failed to access library '/../altera/verilog/max' at "/../altera/verilog/max".

# 

# No such file or directory. (errno = ENOENT)

# ** Error: (vsim-3033) test.vo(84): Instantiation of 'max_io' failed. The design unit was not found.

# 

# Region: /test_vlg_vec_tst/i1

# Searched libraries:

# ** Error: (vsim-19) Failed to access library '/../altera/verilog/max' at "/../altera/verilog/max".

# 

# No such file or directory. (errno = ENOENT)

# c:/altera/13.0sp1/modelsim_ase/altera/verilog/altera

# c:/altera/13.0sp1/modelsim_ase/altera/verilog/altera_mf

# c:/altera/13.0sp1/modelsim_ase/altera/verilog/220model

# c:/altera/13.0sp1/modelsim_ase/altera/vhdl/sgate

# C:/Users/tracy/Documents/test/simulation/qsim/work

# ** Error: (vsim-19) Failed to access library '/../altera/verilog/max' at "/../altera/verilog/max".

# 

# No such file or directory. (errno = ENOENT)

# ** Error: (vsim-3033) test.vo(97): Instantiation of 'max_io' failed. The design unit was not found.

# 

# Region: /test_vlg_vec_tst/i1

# Searched libraries:

# ** Error: (vsim-19) Failed to access library '/../altera/verilog/max' at "/../altera/verilog/max".

# 

# No such file or directory. (errno = ENOENT)

# c:/altera/13.0sp1/modelsim_ase/altera/verilog/altera

# c:/altera/13.0sp1/modelsim_ase/altera/verilog/altera_mf

# c:/altera/13.0sp1/modelsim_ase/altera/verilog/220model

# c:/altera/13.0sp1/modelsim_ase/altera/vhdl/sgate

# C:/Users/tracy/Documents/test/simulation/qsim/work

# ** Error: (vsim-19) Failed to access library '/../altera/verilog/max' at "/../altera/verilog/max".

# 

# No such file or directory. (errno = ENOENT)

# ** Error: (vsim-3033) test.vo(123): Instantiation of 'max_mcell' failed. The design unit was not found.

# 

# Region: /test_vlg_vec_tst/i1

# Searched libraries:

# ** Error: (vsim-19) Failed to access library '/../altera/verilog/max' at "/../altera/verilog/max".

# 

# No such file or directory. (errno = ENOENT)

# c:/altera/13.0sp1/modelsim_ase/altera/verilog/altera

# c:/altera/13.0sp1/modelsim_ase/altera/verilog/altera_mf

# c:/altera/13.0sp1/modelsim_ase/altera/verilog/220model

# c:/altera/13.0sp1/modelsim_ase/altera/vhdl/sgate

# C:/Users/tracy/Documents/test/simulation/qsim/work

# ** Error: (vsim-19) Failed to access library '/../altera/verilog/max' at "/../altera/verilog/max".

# 

# No such file or directory. (errno = ENOENT)

# ** Error: (vsim-3033) test.vo(148): Instantiation of 'max_mcell' failed. The design unit was not found.

# 

# Region: /test_vlg_vec_tst/i1

# Searched libraries:

# ** Error: (vsim-19) Failed to access library '/../altera/verilog/max' at "/../altera/verilog/max".

# 

# No such file or directory. (errno = ENOENT)

# c:/altera/13.0sp1/modelsim_ase/altera/verilog/altera

# c:/altera/13.0sp1/modelsim_ase/altera/verilog/altera_mf

# c:/altera/13.0sp1/modelsim_ase/altera/verilog/220model

# c:/altera/13.0sp1/modelsim_ase/altera/vhdl/sgate

# C:/Users/tracy/Documents/test/simulation/qsim/work

# ** Error: (vsim-19) Failed to access library '/../altera/verilog/max' at "/../altera/verilog/max".

# 

# No such file or directory. (errno = ENOENT)

# ** Error: (vsim-3033) test.vo(160): Instantiation of 'max_io' failed. The design unit was not found.

# 

# Region: /test_vlg_vec_tst/i1

# Searched libraries:

# ** Error: (vsim-19) Failed to access library '/../altera/verilog/max' at "/../altera/verilog/max".

# 

# No such file or directory. (errno = ENOENT)

# c:/altera/13.0sp1/modelsim_ase/altera/verilog/altera

# c:/altera/13.0sp1/modelsim_ase/altera/verilog/altera_mf

# c:/altera/13.0sp1/modelsim_ase/altera/verilog/220model

# c:/altera/13.0sp1/modelsim_ase/altera/vhdl/sgate

# C:/Users/tracy/Documents/test/simulation/qsim/work

# ** Error: (vsim-19) Failed to access library '/../altera/verilog/max' at "/../altera/verilog/max".

# 

# No such file or directory. (errno = ENOENT)

# ** Error: (vsim-3033) test.vo(173): Instantiation of 'max_io' failed. The design unit was not found.

# 

# Region: /test_vlg_vec_tst/i1

# Searched libraries:

# ** Error: (vsim-19) Failed to access library '/../altera/verilog/max' at "/../altera/verilog/max".

# 

# No such file or directory. (errno = ENOENT)

# c:/altera/13.0sp1/modelsim_ase/altera/verilog/altera

# c:/altera/13.0sp1/modelsim_ase/altera/verilog/altera_mf

# c:/altera/13.0sp1/modelsim_ase/altera/verilog/220model

# c:/altera/13.0sp1/modelsim_ase/altera/vhdl/sgate

# C:/Users/tracy/Documents/test/simulation/qsim/work

# ** Error: (vsim-19) Failed to access library '/../altera/verilog/max' at "/../altera/verilog/max".

# 

# No such file or directory. (errno = ENOENT)

# Loading work.test_vlg_sample_tst

# ** Error: (vsim-19) Failed to access library '/../altera/verilog/max' at "/../altera/verilog/max".

# 

# No such file or directory. (errno = ENOENT)

# Loading work.test_vlg_check_tst

# Error loading design

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Altera_Forum
Honored Contributor II
‎12-27-2017 12:31 AM
2,987 Views

Hi, 

 

Check the below thread which discuss on same issues. 

https://alteraforum.com/forum/showthread.php?t=44213 

 

To work around this problem, perform the following steps 

Make the file <Quartus II installation directory>\modelsim_ase\modelsim.ini writable. For example on Windows, right-click the file, select properties from the context menu and turn off the read-only option 

Add the following line to modelsim.ini: 

max7000s = /../altera/verilog/max 

 

Best Regards, 

Anand Raj Shankar 

(This message was posted on behalf of Intel Corporation)
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