a simple example. You have a synchronizer register in a VHDL entity and want a set_false_path statement added for each instance in the design automatically. As SDC uses hierarchical object names, the entity name must be unique.
ARCHITECTURE rtl OF ce_sync IS SIGNAL ce_toggle : STD_LOGIC := '0'; attribute altera_attribute : string; attribute altera_attribute of rtl : architecture is "-name SDC_STATEMENT ""set_false_path -from [get_registers *ce_sync:*|ce_toggle]""";
Multiple SDC statements can be placed in the attribute statement by string concatenation.
Guess you should follow the instructions in Quartus manual "Apply altera_attribute to an Entity". Example:
(* altera_attribute = "-name AUTO_SHIFT_REGISTER_RECOGNITION OFF" *) module my_entity(…) ;
There's different syntax for Verilog-1995 and Verilog-2001/SystemVerilog. The latter places the attribute before the module declaration. Please review the user manual.
Correction: Still available at intel.com, but new link https://www.intel.com/content/www/us/en/support/programmable/articles/000078356.html?wapkw=How%20do%20I%20embed%20timing%20constraints%20in%20my%20HDL%20file
Yes that is correct. I believe it's because the altera_attribute option is added to the project by Quartus during synthesis, meaning that it's added the same time the hierarchy is formed and compiled.
Do you have anymore questions?
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