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SDC input constraints for DDR ADC newbie question

Oliver_I_Sedlacek
New Contributor III
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I'm trying to set the SDC constraints for the DDR input from an LTC2386 ADC and I need a bit more guidance. I've watched Intel's tutorial video at https://www.youtube.com/watch?v=GItefNliYpM so with length matched clock and data traces clock skew should be zero. How do I do constraints for both positive and negative edges? Should I have two completely separate constraints?

TIA

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AdzimZM_Intel
Employee
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Hello,


"Should I have two completely separate constraints?"

  • Yes, typically need to consider both the positive and negative edges separately because data is sampled on both edges of the clock.


"How do I do constraints for both positive and negative edges?"

  • From my understanding, the idea roughly is like this,
    • From data constraint, you need to identify the setup and hold times for the data relative to both the positive and negative edges of the clock.
    • Use set_input_delay constraints to specify the setup and hold times for the data signals relative to clock edges.
    • And then, you prolly need to do group and I/O contraints.
    • So your SDC will have set input/output delay for positive and negative respectively


Regards,

Adzim


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Oliver_I_Sedlacek
New Contributor III
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Thanks, I'll dive deeper into that. I'm getting a lot of warnings that seem to do with separate p and n pins of the LVDS pair so I guess I need to figure out how to target the non-LVDS signals.

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