Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
17253 Discussions

SDC warnings when compiling SoC/HPS devices

Altera_Forum
Honored Contributor II
2,641 Views

Using Quartus II (15.1) and QSys to generate "soc_system.qsys". It contains a hps_0 instance. When the Qsys HDL files is generated it generates "soc_system/synthesis/submodules/soc_system_hps_0_hps_io_border.sdc". It contains a long list of statements like 

 

set_false_path -from * -to set_false_path -from * -to  

 

Quartus finds this .sdc file and tries to run it, and fails: 

 

Info (332104): Reading SDC File: 'soc_system/synthesis/submodules/soc_system_hps_0_hps_io_border.sdc' Warning (332174): Ignored filter at soc_system_hps_0_hps_io_border.sdc(1): hps_io_hps_io_emac1_inst_TX_CLK could not be matched with a port Warning (332049): Ignored set_false_path at soc_system_hps_0_hps_io_border.sdc(1): Argument <to> is an empty collection Info (332050): set_false_path -from * -to Warning (332174): Ignored filter at soc_system_hps_0_hps_io_border.sdc(2): hps_io_hps_io_emac1_inst_TXD0 could not be matched with a port Warning (332049): Ignored set_false_path at soc_system_hps_0_hps_io_border.sdc(2): Argument <to> is an empty collection Info (332050): set_false_path -from * -to  

 

The reason is that the ports names in the .sdc does not match any top-level ports, and as such all ports on the HPS system fails to match and creates massive number of warnings in the output. Is there a way to suppress this? How is this intended to work?
0 Kudos
0 Replies
Reply