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SPI Slave to Avalon Master Bridge design example questions/help

Honored Contributor II

I have setup the MAX 10 design example that places both a NIOS II processor and an [SPI Slave to Avalon Master Bridge] on the same FPGA chip. The code is run from the flash memory of my DE10 Lite FPGA board. These are two Qsys projects that talk back and fourth betweem themselves via spi. The NIOS II processor runs some code that creates a ramdom pattern in memory and "sends" it to the slave. The sending process involves creating a packet, sending it over spi, and once received by the slave, THe slave process decodes the packet, and writes to to on the on chip ram. The project works pretty good.  





My goal is to split it in 2. I want to have the master spi code runnign on a Raspberri Pi using some of the software components in the project to packane a message and send it over spi, to the slave running on the fpga. The slave, like in the origional project, will decode the pacet and write it to on board ram.  







I expect to have the master constantly writing data. And the slave constantly processing that data/memory. 

I expect to add another FPGA process to read the memory that is being controlled from the raspberri pi. 



Anyways, I'm having some problems.... 



The first, the message from the raspberri pi goes over the spi bus to the fpga but the results are different than when both the master and slave were on the same chip?  



First question, should there be anying inherantly wrong with this?  



Second question, is the Avalob bus/memory robust enough that i can have on process write to it and another read from it? How would it be ste to be used by only once proc ess at the same time (inside the FPGA). I haven't written the other process yet. 



Thirs question, in an effort to see what signals are being sent in the origional project. I would like to break outthe spi wires to fpga pins and see whats happening on my oscilliscope. The origional MAX 10 design example has the 2 qsys components wired together as in  





nios_spi_master nios_spi_master ( 

.clk_clk (IN_CLOCK), 

.reset_reset_n (IN_RESET_N), 

.led_export (led[7:4]), 

.spi_MISO (MISO), 

.spi_MOSI (MOSI), 

.spi_SCLK (SCLK), 

.spi_SS_n (SS_N) 




spi_slave spi_slave ( 

.clk_clk (IN_CLOCK), 

.reset_reset_n (IN_RESET_N), 

.spi_mosi_to_the_spislave_inst_for_spichain (MOSI), 

.spi_nss_to_the_spislave_inst_for_spichain (SS_N), 

.spi_miso_to_and_from_the_spislave_inst_for_spichain (MISO), 

.spi_sclk_to_the_spislave_inst_for_spichain (SCLK), 

.switch_export (IN_SWITCH), 

.led_export (led[3:0]) 





I wish to take a line like MISO and send it to an FPGA pin. I'm having a problem writing the vhdl code for this as it appears nothing is happening on the line. 


Any help would be much appreciated. I am very new to this.
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