I'm trying to simulate SPI slave to Avalon master bridge core. I can see that when I issue a read transaction then under some conditions the start symbol 0x7c in the core response is lost. It is acknowledged by the MISOctl module but it doesn't appear in the output shift register rdshiftreg. It looks like a sync problem between sclk and system clock domains. Is it something wrong with my setup or is it really a bug in the IP?
Sorry for getting back to you rather late. Can you let me know which module are you simulating in modelsim? Which library can I find this module in?
Can you also let me know which version of Quartus are you using?
I use Quartus Prime Version 20.1.1 Lite Edition with Modelsim Intel FPGA Starter Edition 2020.1.
I use spi_test.do as a simulation script. Top level module is spi_test_tb, which instantiates spi_test module and a Qsys testbench with SPI Slave to Avalon Master Bridge IP as a DUT and BFMs. Spi_test module is to provide stimuli on SPI bus.
We did not receive any response to the previous question/reply/answer that I have provided, thus I will put this case to close pending. Please post a response in the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you with your follow-up questions.
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