Hi All,What timing constraints should be applied for the synchronizers? 1) false path from a clock pin of the first flop to D-pin of the second/last flop 2) what about the multicycle path? should it be applied for the synchronizers? Thank you!
1. You only need the false path between the registers that actually cross the clock domain. Unlike Xilinx, who insist you time everything from pin to pin, making getting the paths correct annoying and a little tedious, Altera have a get_keepers function, that make it easier to fetch objects. Usually its often easier just easier to set a -to or -from for a single end-point rather than both ends.set_false_path -to [get_keepers */my_ent/cdc_reg_clkB] 2. Multi-cycle paths should only be set on registers that actually have a multicycle path. Synchronisers often do not. Are you talking about some specific design?
No, A multi-cycle path applies for a single path where a register is only active (enabled) for a single clock cycle with other clock cycles in between. Eg, you have a clock enable that is only high every 3 clock cycles, then you know you have a 3 cycle MCP, with 2 clocks of hold. In synchronisers, each register is clocked at full rate, so need to be timed as normal.You may have MCPs if you have some slower form of hand-shaking that has a known timing relationship, then MCPs may be valid. But if it is a standard 2 reg synchroniser, only false paths are valid (or maybe a relaxed max delay constraint to prevent the registers being placed too far from each other).
no, a false path will override a max delay. A false path will probably be fine, but theres no guarantee the placer wont put the endpoints at opposite corners of the chip. Using a max delay (with a very relaxed constraint) should ensure they're reasonably close.