i have a simple sv code, which has assertions
module top(input [2:0] in1, input [2:0] in2, output [3:0] out1, input clk);
parameter p1 = 4;
parameter p2 = 5;
reg [3:0] out1_reg;
always @(posedge clk) begin
assert(p1 == p2)
assign out1 = out1_reg;
//assign out1 = in1+ in2;
I have enable the asseriotion, under assignements->settings->compiler settings-> advanced options.
when i run the above code i dont see any error message.
and i see assertion is supported
am I missing something, while using assertion?
- SV assertions
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