I have a Qsys design using PCIe hard IP with an Avalon MM slave for Stratix 10, the fitter terminates during placement operations after reporting over 1000 occurrences of the following error:
Error(170079): Cannot place node "[node name]" of type Combinational cell
The only relevant resource I've found is https://www.intel.com/content/altera-www/global/en_us/index/support/support-resources/knowledge-base... which is the same error but for DSP cells, not combinational. Even so, I tried to rerun the tools with DSP inference turned off ([DSP Block Balancing = Logic Elements] in the synth settings) and the same fitter errors were observed. Any assistance would be greatly appreciated.
Verify that you are targeting the correct Quartus project and device in Platform Designer. If so, does the system generate successfully in Platform Designer before even trying to compile in Quartus?
Do you recognize the nodes that the tool is saying cannot be placed in your design? What are they?
Thanks for your reply. I verified the target device - it is correct. I commented out the main functionality of the Avalon MM slave and connected its input to its output so as to make a simple memory module, this compiled and ran correctly in the hardware (verified by several writes and reads performed on a desktop linux host). After reverting the Avalon MM slave to its intended functionality, the same errors occur. The Platform Designer generates the design successfully, it reports no errors but gives several warnings of the form "...The value of parameter cdr_pll_powermode_ac_bbpd cannot be automatically resolved. Valid values are: bbpd_ac_bti bbpd_ac_off bbpd_ac_on.", these warnings do not seem to affect functionality and they appear to be unrelated to the fitter error 170079.
The nodes which cannot be placed are mostly adders (labeled "add_1~####") and shifters (labeled "shift_left_0~####"), there are also some register cells (i.e. type "register cell" rather than "combinational cell") which I didn't notice when I wrote my original post, these are labeled "~RTM_####". Some but not all of the error messages end with "... cell with location constraints CUSTOM_REGION_[coordinates] from User-Defined Logic Lock Region and Promoted Clock Region". I opened the Logic Lock Regions window and there are no regions listed there. To make the design I generated an example design from the PCIe Hard IP Platform Designer, then I opened the example design and opened the top level Qsys design in the Platform Designer; in the Platform Designer I made a new Avalon MM slave component using a custom VHDL file and connected it to the PCIe Hard IP Avalon MM master... perhaps the Quartus-generated example design includes some placement constraints that I don't know about?
This issue is known and understood and that the LAB height for some carry chains can be higher than the clock tree, resulting in the fitter error. The issue is fixed in the Intel Quartus Prime Pro edition software version 19.3.