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Honored Contributor I
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Serdes fitter placement ERROR in Quartus II 17.1

I got a fitter placement error in Quartus II 17.1 and the problem as below: SW VERSION: Quartus II 17.1 Device: 5CGTFD7D5F27C7 Background and problem: There are two serdes modules in our design, one is custom serdes IP with 1 channel. And another is RapidIOx2 IP. I would like to merge the TX PLL for the two Serdes modules in my design, so I follow the rules: Our Device is CycloneV GT D7(5CGTFD7D5F27C7) and serdes channel as below: One configuration can pass fitter: channel 0-> custom serdes; channel 1-> reserve for PLL; channel 2-> RapidIOX2[0]; channel 3-> RapidIOX2[1]; channel 4-> null; channel 4-> null; But this Configuration will fail at fitter (only difference is the pin assignment change on RapidIO) channel 0-> custom serdes; channel 1-> reserve for PLL; channel 2-> null; channel 3-> null; channel 4-> RapidIOX2[0]; channel 4-> RapidIOX2[1]. Where the RapidIO PLL should be merged with custom IP PLL and only one PLL placed at channel1. But now it seems they are not merged. The fitter error message as below: ----------------------------------------------------start of error message---------------------------------------------------------- "Error (14566): The Fitter cannot place 1 periphery component(s) due to conflicts with existing constraints (1 Channel PLL(s)). Fix the errors described in the submessages, and then rerun the Fitter. The Intel FPGA Knowledge Database may also contain articles with information on how to resolve this periphery placement failure. Review the errors and then visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number. Error (175020): The Fitter cannot place logic Channel PLL that is part of RapidIO (IDLE1 up to 5.0 Gbaud) srio_serdes_rapidio_0 in region (0, 19) to (0, 25), to which it is constrained, because there are no valid locations in the region for logic of this type. Info (14596): Information about the failing component(s): Info (175028): The Channel PLL name(s): srio_top:inst_srio_top|srio_serdes_ip:inst_sriox2|srio_serdes:inst_srio_serdes|srio_serdes_rapidio_0:rapidio_0|srio_serdes_rapidio_0_rio:srio_serdes_rapidio_0_rio_inst|srio_serdes_rapidio_0_riophy_xcvr:riophy_xcvr|srio_serdes_rapidio_0_riophy_gxb:riophy_gxb|altera_xcvr_custom:srio_serdes_rapidio_0_riophy_gxb_inst|av_xcvr_custom_nr:A5|av_xcvr_custom_native:transceiver_core|av_xcvr_plls:gen.av_xcvr_native_insts[0].gen_tx_plls.gen_tx_plls.tx_plls|pll[0].pll.cmu_pll.tx_pll Error (16234): No legal location could be found out of 6 considered location(s). Reasons why each location could not be used are summarized below: Error (178004): Could not find location for the Channel PLL that enable routing of bonding clock lines (6 locations affected) Info (175029): Channel PLL containing CHANNELPLL_X0_Y13_N32 Info (175029): Channel PLL containing CHANNELPLL_X0_Y21_N32 Info (175029): Channel PLL containing CHANNELPLL_X0_Y25_N32 Info (175029): Channel PLL containing CHANNELPLL_X0_Y33_N32 Info (175029): Channel PLL containing CHANNELPLL_X0_Y37_N32 Info (175029): Channel PLL containing CHANNELPLL_X0_Y45_N32 Info (175013): The Channel PLL is constrained to the region (0, 21) to (0, 25) due to related logic Error (11802): Can't fit design in device. Modify your design to reduce resources, or choose a larger device. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number. Error: Quartus Prime Fitter was unsuccessful. 5 errors, 105 warnings Error: Peak virtual memory: 1899 megabytes Error: Processing ended: Fri Jun 15 12:09:28 2018 Error: Elapsed time: 00:03:30 Error: Total CPU time (on all processors): 00:03:30 Error (293001): Quartus Prime Full Compilation was unsuccessful. 7 errors, 1222 warnings" ----------------------------------------------------end of error message---------------------------------------------------------- So may I know how any way to make the second configuration work. Thx to all.

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