library IEEE;use IEEE.std_logic_1164.all; use IEEE.numeric_std.all;entity shift_reg is port( d : in std_logic; clk : in std_logic; rst_bar : in std_logic; q : out std_logic_vector(7 downto 0) );end shift_reg;architecture post_vhdl_08 of shift_reg is begin process(clk, rst_bar) variable q_int : std_logic_vector(7 downto 0); begin if rst_bar = '0' then q_int := (others => '0'); elsif rising_edge(clk) then q_int := q_int(6 downto 0) & d; end if; q <= q_int; end process;end post_vhdl_08;
I've implemented a shift left register with serial input and parallel output using a "slice" to implement the shift; but I can't figure out how to implement the same logic using an overloaded shift operator: 'sll' (shift left logical) operator. Thank you all for any help you can offer.
