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MoZdk
Novice
823 Views

Should Quartus 18.1 support FF creation by this: Q <= D when rising_edge(CLK); The D and CLK are input ports on a module, and Q is a output port. The Quartus 18.1 breaks with internal error due to this construction.

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5 Replies
sstrell
Honored Contributor II
63 Views

That's not standard synthesizable Verilog or VHDL, so of course it will not work.

Tricky
New Contributor II
63 Views

@sstrell​ 

 

While it is not officially supported (I cant find it in any coding guidelines) it has been supported by many tools for many years.

In VHDL, one liners like this actually infer a process sensitive to all signals on the RHS. So

 

q <= d when rising_edge(clk);

 

is functionally identical to

process(clk, d) -- D not needed, but it is needed for full equivolence to one liner. begin if rising_edge(clk) then q <= d; end if; end process;

 

MoZdk
Novice
63 Views

Thanks for the answer.

 

It may not be supported coding style for inference of flip-flops, and it is used very little, if at all in practice, so may be OK not to support in Intel coding guidelines.

 

However, the coding style makes Quartus 18.1 break with internal error, which indicates a bug in the tool.

 

? Any suggestion for how I can report this bug ?

 

PLehm
Beginner
63 Views

This code line is standard synthesizable code.

It was specified in IEEE Std. 1076.6-2004 Clause 6.1.3.5

 

6.1.3.5 Edge-sensitive storage using concurrent signal assignment statements

A concurrent conditional signal assignment statement may be used to model an edge-sensitive storage element

provided that the assignment can be mapped to a process that adheres to the rules in 6.1.3.1.

 

Example:

COND_SIG_ASSGN: Q <= '0' when RESET = '1' else '1' when SET = '1' else A when ASYNC_LOAD = '1' else D when CLOCK'EVENT and CLOCK = '1';

 

More over it was supported by previous Quartus versions as this tool was called "Altera Quartus II".

Even if it's an unsupported syntax, a tool should never crash.

 

In addition, this syntax is supported by all competitors (I'm listing only synthesizer tools):

  • Xilinx ISE
  • Xilinx Vivado
  • Lattice LSE
  • Synopsys Simplify PRO

 

Kind regards

Patrick Lehmann

 

Vice-Chair of the IEEE P1076 Working Group

 

MoZdk
Novice
63 Views

I tried to recreate the problem, in order to do a bug report in this issue:

https://forums.intel.com/s/question/0D50P000045bbhASAQ/how-to-report-a-bug-in-the-quartus-tool

However, I was unable to recreate the problem again, so for now I cant look further into this with respect to the Quartus error.

 

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