Question about Signal Tap Logic Analyzer feature (capacity).
In the User Guide, the feature is described as follows.
- Up to 2,048 channels per logic analyzer instance
Does "2,048 channels" mean the number of signals that can be monitored ?
(the bit width of each channel is not defined ?)
Or does "2,048 channels" mean the total number of bits ?
(Signal Tap can probe 2048-bit ?)
The limitation of Xilinx 's ILA(Integrated Logic Analyzer) is as follows.
- The maximum number of Probe ports is 1,024
and the maximum width of each Probe port can be up to 4,096.
However, the total number of bits (sum of all probe ports)
cannot exceed 65,536 bits.
Is the limitation on Signal Tap better than Xilinx 's ILA ?
Thank you for your comment.
What is the limitation of the bit width of each channel(signal) ?
4096-bit per signal ? (Xilinx's case is 4096-bit per signal)
And, if there is the limitation of the total number of bits (sum of all channels),
could you please give me the information ? (Xilinx's limitation is total 65,536-bits)