Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
Announcements
Intel Support hours are Monday-Fridays, 8am-5pm PST, except Holidays. Thanks to our community members who provide support during our down time or before we get to your questions. We appreciate you!

Need Forum Guidance? Click here
Search our FPGA Knowledge Articles here.
15547 Discussions

[Signal] unassigned node -> what does it mean?

Altera_Forum
Honored Contributor II
878 Views

Hi All, 

 

In the SignalTap, what does it mean "unassigned node"? See the snapshot below.  

 

https://alteraforum.com/forum/attachment.php?attachmentid=14666&stc=1  

 

Thank you!
0 Kudos
0 Replies
Reply