SignalTap Analyser corrupted signals

[Altera_Forum]

Hi there,  

I am running the standalone SignalTap Analyser as I need to debug a board offshore. I created a SOF file along with a STP file (SignalTap analyser signals). I was able to load the SOF file and to run the SignalTap analyser from home. To my surprised, there are some random corrupted signals feed to the SignalTap Analyser. I get most of the time the signal that I expect but sometimes, it is like the bits on a bus get swapped. I have seen this problem multiple times. The only explanation, I can think of, is that the information received on the computer (where I run the SignalTap Analyser) is corrupted. As an example, I use only bits[3:0] of an 8-bit register, the bits[7:4] are always driven to 0. I can see, sometimes, a very high frequency noise on the bit 7. I am sure that the design only drive a constant 0 on that bit. This situation can be seen on many other signals. For instance, I can see that some of the bits of a bus, which run at low speed, start toggling at very high speed while most of the other bits are still running at low speed. I have been using this tool for quite a long time and I have never seen this behaviour. I cannot see it at home either, only offshore.  Since I can see, most of the time, valid behaviour on all the signals, I tend to assume that the information on the FPGA has been downloaded properly. It also means that the JTAG port (that I used to program the device and to read the SignalTap information from) must be working as well. I have also used the same technique before with success. When this corruption happens, the FPGA "seems" to be working fine. The FPGA is running just fine, while I read the SignalTap Analyser data. I used the same revision for both standalone tools (Programmer and SignalTap Analyser) at home and offshore. The revision is 13.1.0.162 (I know this is an old version but that was all they could install offshore). This revision works perfectly fine at home anyway.  Any suggestion on the possible causes of this strange behaviour? P.S.: I have attached a picture of one of the corrupted bus, the LSB bits are expected to toggle at high speed, but not the bit [9]. Left and right side of the bit [9] fast toggling (circled in black) represent the normal behaviour. The two signals circled in blue is an "abnormal" behaviour.

[Altera_Forum]

--- Quote Start ---  Hi there, I am running the standalone SignalTap Analyser as I need to debug a board offshore.   --- Quote End ---    What's your hardware, as this could be some sort of a clocking issue as well. Are you getting any sort of timing errors? And is your SignalTap clock lined up correctly with the data?

[Altera_Forum]

There is no timing issue with the netlist that I used for this experiment. As for the clock for the SignalTap, it is using the JTAG port and, as far as I know, the JTAG is working fine in their application. I am using a very similar board here and there is no issues at all with the SignalTap Analyser. 

Finally, for the hardware, it is a very sophisticated board, so it is hard to describe it. A very similar board is currently used and has being shipped to customer for many years.

[Altera_Forum]

What kind of JTAG interface are you using and which OS do you have on the PC running Signaltap? I've seen that kind of problems when running some USB blaster clones under Linux. But the same clone under Windows or a real USB blaster under Linux work fine.

[Altera_Forum]

--- Quote Start ---  What kind of JTAG interface are you using and which OS do you have on the PC running Signaltap? I've seen that kind of problems when running some USB blaster clones under Linux. But the same clone under Windows or a real USB blaster under Linux work fine.  --- Quote End ---    Sorry for the late reply. I have been away for a little while. I know that they are using a Windows machine but I will check with them about the version and about the USB blaster as well. I will get back to you soon. Thanks for your help, Pierre