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Altera_Forum
Honored Contributor I
2,310 Views

SignalTap II issue

Hello, 

 

Here is debounce state machine: 

 

module debounce_explicit(input clk, reset, sw, output reg db_level, db_tick); //symbolic state declaration localparam zero = 2'b00, wait0 = 2'b10, one = 2'b11, wait1 = 2'b01; // number of counter bits (2'N * 20ns = 40ms) localparam N = 21; //localparam N = 15; // signal declaration reg state_reg, state_next; reg q_reg; wire q_next; wire q_zero; reg q_load, q_dec; // FSMD state & data registers always @(posedge clk, posedge reset) if (reset) begin state_reg <= zero; q_reg <= 0; end else begin state_reg <= state_next; q_reg <= q_next; end // FSMD data path (counter) next—state logic assign q_next = (q_load) ? {N{1'b1}} : ((q_dec) ? q_reg - 1 : q_reg); // status signal assign q_zero = (q_next == 0); // FSMD control path next—state logic always @* begin state_next = state_reg; // default state: the same q_load = 1'b0; // default output: 0 q_dec = 1'b0; // default output: 0 db_tick = 1'b0; // default output: 0 case (state_reg) zero: begin db_level = 1'b0; if (sw) begin state_next = wait1; q_load = 1'b1; end end wait1: begin db_level = 1'b0; if (sw) begin q_dec = 1'b1; if (q_zero) begin state_next = one; db_tick = 1'b1; end end else // sw==0 state_next = zero; end one: begin db_level = 1'b1; if (~sw) begin state_next = wait0; q_load = 1'b1; end end wait0: begin db_level = 1'b1; if (~sw) begin q_dec = 1'b1; if (q_zero) state_next = zero; end else // sw==l state_next = one; end default: state_next = zero; endcase end endmodule  

 

And here is SignalTap simulation 

http://www.alteraforum.com/forum/attachment.php?attachmentid=13218&stc=1  

 

After 2st firing of the input sw the "state machine" frozes definitely in "00" state. 

Moreover, after 1st sw firing, the "state machine" value is displayed in symbolic interpretation in SignalTap II, i.e. zero, wait0, one, wait1

After 2nd sw firing this symbolic interpretation disappears ... leaving place to numeric interpretation, i.e. 0 (as shown on the above image). 

 

So I have 2 questions: 

  • why symbolic interpretation disappears 

  • is it possible to put into SignalTap the signals that present in the source code in order to debug "system machine" misbehavior. Actually only few signals are available for SignalTap. 

 

 

Thanks in advance
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13 Replies
Altera_Forum
Honored Contributor I
121 Views

Unless otherwise specified by synthesis attribute, the state machine is coded in default "one hot" style, the state is represented by four register bits. Respectively the state machine can fall into illegal states. This can happen if the input signals to the state machine involve timing violations, e.g. asynchronous external signals. Instead of "one hot" you get zero or multiple hot state bits. At worst case, the state machine may be stuck in such an illegal state. 

 

I don't remember how an illegal state is shown in signal tap, but I expect it has no symbolic name. 

 

You should either care that the timing violation is fixed or if this isn't possible under all circumstances, specify safe state machine logic that recovers automatically from illegal states.
Altera_Forum
Honored Contributor I
121 Views

As far as the state names in the captured data, you can either manually create a mnemonic table by right-clicking in the Node list on the Setup tab and filling in the names you want and the bit patterns that should be used. Then, on the Data tab, right click the state signals and set the radix to the mnemonic table you created. There is also an option on the right-click menu in the Node list on the Setup tab to create mnemonic tables for state machines. And as mentioned, if you are going to an illegal state, there will be no name displayed for it.

Altera_Forum
Honored Contributor I
121 Views

You need a base clock constraint, create_clock, in your .sdc file for the design, as well as any related I/O timing constraints using set_input_delay and set_output_delay.

Altera_Forum
Honored Contributor I
121 Views

 

--- Quote Start ---  

You need a base clock constraint, create_clock, in your .sdc file for the design, as well as any related I/O timing constraints using set_input_delay and set_output_delay. 

--- Quote End ---  

 

 

Here is the content of the .SDC file: 

create_clock -name clk -period 20.0 clk derive_pll_clocks derive_clock_uncertainty 

 

Concerning I/O timing constraints, I din't find how to setup them ... in the quartus prime standard edition handbook, vol. 3, "Timing Constraints" chapter there is very few information on this topic. 

In my design there are (except clock) only 3 inputs: 2 buttons and 1 switch and 4x7 outputs (4 7-segment displays). 

Is there some information how to setup such staff. 

 

Anyway, here is the content of the TimeQuest "Unconstrained Paths Summary": 

https://www.alteraforum.com/forum/attachment.php?attachmentid=13242  

 

Apparently the luck of the input constraints still prevents the design to work correctly. Here is SignalTap simulation result - the state machine changes its state from "wait1" to NOSTATE (blue line marker) without any visible cause: the state machine "follows" the sw signal, but as you can state, the sw is constant when state changes from "wait1" to NOSTATE. 

https://www.alteraforum.com/forum/attachment.php?attachmentid=13243  

 

Thanks 

 

P.S. Also there is a strange clock altera_reserved_tck (that I didn't specified) in the clock list .
Altera_Forum
Honored Contributor I
121 Views

Hi,  

 

I did not read all your posts but from firts glance you have timing related problems. First try to synchronize your SW signal to clk domain with a two-stage shift-register only then feed it to state machine. You can add state machine states in signaltap by clicking right mouse button and chossing "Add state machine nodes.."
Altera_Forum
Honored Contributor I
121 Views

 

--- Quote Start ---  

Hi,  

 

I did not read all your posts but from firts glance you have timing related problems. First try to synchronize your SW signal to clk domain with a two-stage shift-register only then feed it to state machine. You can add state machine states in signaltap by clicking right mouse button and chossing "Add state machine nodes.." 

--- Quote End ---  

 

Thanks for suggestion. 

This example I took from this book: https://www.amazon.com/embedded-design-processor-verilog-examples/dp/1118011031/ref=sr_1_1?s=books&i... 

 

So, undoubtedly, it was tested ... although the reference card in this book was altera de1 based on a cyclone ii ep2c20, and I use terasic de1 soc, I don't think that it could make impact on the code functionality. 

Concerning states of state machine, they are already added in SignalTap ... at least you can see "zero" and "wait1" on the waveforms ... until the moment when state machine "crashes" for some unexplained reasons. At that moment the state of the state machine is displayed as 0

 

For the moment I'm trying to understand what does "input constraint" mean with respect to an input that is driven by an external switch.
Altera_Forum
Honored Contributor I
121 Views

I dont think that you need any input constrains for external switch since it is asynchronous signal. Usually for such signals i use set_false_path command:  

set_false_path -from [get_ports SW] 

 

 

--- Quote Start ---  

crashes" for some unexplained reasons. 

--- Quote End ---  

 

One reason I can think about is - metastability because asynchronous SW signal. I always try to avoid using such asynchronous signals directly without any synchronization logic.
Altera_Forum
Honored Contributor I
121 Views

As mentioned, use false paths for switches and LEDs. altera_reserved_tck is the JTAG clock. You don't need to constrain this.

Altera_Forum
Honored Contributor I
121 Views

 

--- Quote Start ---  

As mentioned, use false paths for switches and LEDs. altera_reserved_tck is the JTAG clock. You don't need to constrain this. 

--- Quote End ---  

 

Hello, 

Here is the last version of .sdc file (if I correctly understood the suggestion): 

create_clock -name clk -period 20.000 derive_clock_uncertainty# set_input_delay -clock { clk } 5 # set_input_delay -clock { clk } 5 # set_input_delay -clock { clk } 5 set_false_path -from set_false_path -from set_false_path -from  

 

Unfortunately it didn't help: input signal on sw port puts the "state machine" in undefined state. 

Moreover, there are still unconstrained inputs ... is it correct ? In this design there are 4 inputs (2 buttons, 1 switch, 1 clock) and all input ports are present in .sdc

http://www.alteraforum.com/forum/attachment.php?attachmentid=13257&stc=1  

 

Are there some options that I could add into .sdc file in order to proceed with full timing analysis ? 

 

Concerning metastability issue, that could be the cause of problem, I have a couple of questions: 

  1. How to properly setup "Report Metastability" in TimeQuest in order to get reliable overview of metastability issues. Actually when I run "Report Metastability", the "non-calculated" value is filled everywhere in the report 

  2. The metastability issue can be only managed with "design-related" means (e.g. add synchronization flip-flops in the verilog-coded module just after input ports, and then apply thy synchronizer outputs to state machine) or there are some options in Quartus, that allow to do it automatically (e.g. specify in some way a particular input port as port that requires synchronization). In this regard assignment editor could be evoked: the Assignment Name column has a collection of different values, including, for example, synchronizer identification. So, resuming ... the synchronization chain can be added only in VHDL/Verilog or also via some option in assignment editor

 

Thanks
Altera_Forum
Honored Contributor I
121 Views

 

--- Quote Start ---  

Moreover, there are still unconstrained inputs ... is it correct ? In this design there are 4 inputs (2 buttons, 1 switch, 1 clock) and all input ports are present in .SDC. 

--- Quote End ---  

 

 

Run "Report Ignored Constraints" command in TimeQuest to see if all your SDC commands are accepted. 

After running "Report Unconstrained Paths" check which actual ports are unconstrained (In Report window see Unconstrained Paths -> Setup Analysis -> Unconstrained Input Ports or Unconstrained Output Ports). This way you will find out which ports are left unconstrained or there is some error in your SDC file.  

 

I am guesing that you will find that those two input ports are altera_reserved_tdi and altera_reserved_tms. You can also use set_false_path for those ports. For JTAG i use: 

 

create_clock -period "10 MHz" -name altera_reserved_tck [get_ports altera_reserved_tck] 

set_false_path -from [get_ports {altera_reserved_tdi}] 

set_false_path -from [get_ports {altera_reserved_tms}] 

set_false_path -to [get_ports {altera_reserved_tdo}] 

# Specify the JTAG clock in a group 

set_clock_groups -asynchronous -group altera_reserved_tck  

 

 

--- Quote Start ---  

How to properly setup "Report Metastability" in TimeQuest in order to get reliable overview of metastability issues. Actually when I run "Report Metastability", the "non-calculated" value is filled everywhere in the report 

--- Quote End ---  

 

 

I think you have to set Synchronizer identification option to AUTO in Settings -> TimeQuest Timing Analyzer. 

 

 

--- Quote Start ---  

The metastability issue can be only managed with "design-related" means (e.g. add synchronization flip-flops in the verilog-coded module just after input ports, and then apply thy synchronizer outputs to state machine) or there are some options in Quartus, that allow to do it automatically (e.g. specify in some way a particular input port as port that requires synchronization). In this regard Assignment Editor could be evoked: the Assignment Name column has a collection of different values, including, for example, Synchronizer Identification. So, resuming ... the synchronization chain can be added only in VHDL/Verilog or also via some option in Assignment Editor ? 

--- Quote End ---  

 

 

Yes synchronization chain can be added only in VHDL/Verilog. Synchronizer Identification option prevents synchronization chain from optimizations and enables MTBF analysis.
Altera_Forum
Honored Contributor I
121 Views

 

--- Quote Start ---  

Run "Report Ignored Constraints" command in TimeQuest to see if all your SDC commands are accepted. 

After running "Report Unconstrained Paths" check which actual ports are unconstrained (In Report window see Unconstrained Paths -> Setup Analysis -> Unconstrained Input Ports or Unconstrained Output Ports). This way you will find out which ports are left unconstrained or there is some error in your SDC file.  

 

I am guesing that you will find that those two input ports are altera_reserved_tdi and altera_reserved_tms. You can also use set_false_path for those ports. For JTAG i use: 

 

create_clock -period "10 MHz" -name altera_reserved_tck [get_ports altera_reserved_tck] 

set_false_path -from [get_ports {altera_reserved_tdi}] 

set_false_path -from [get_ports {altera_reserved_tms}] 

set_false_path -to [get_ports {altera_reserved_tdo}] 

# Specify the JTAG clock in a group 

set_clock_groups -asynchronous -group altera_reserved_tck  

 

--- Quote End ---  

 

 

Yes, it's the case, the unconstraiuned inputs are altera_reserved_tdi and altera_reserved_tms

Concerning constraints for JTAG signals is it necessary to create altera reserved_clk, as it's already present ? 

https://www.alteraforum.com/forum/attachment.php?attachmentid=13258  

Thanks
Altera_Forum
Honored Contributor I
121 Views

 

--- Quote Start ---  

I think you have to set Synchronizer identification option to AUTO in Settings -> TimeQuest Timing Analyzer. 

--- Quote End ---  

 

I've checked ... this option is set to auto, but metastability values still aren't calculated 

 

https://www.alteraforum.com/forum/attachment.php?attachmentid=13259
Altera_Forum
Honored Contributor I
121 Views

Finally, Synchronization Register Chains resolved the problem. 

I applied 2 flip-flops to sw input: 

reg sw1, sw2; DFF sync1 (.d(sw), .clk(clk), .clrn(1'b1), .prn(1'b1), .q(sw1)); DFF sync2 (.d(sw1), .clk(clk), .clrn(1'b1), .prn(1'b1), .q(sw2));  

 

and then applied sw2 to state machine (instead of sw). 

However the signals sw1 and sw2 aren't accessible in signaltap ... only sync1, sync2

I suppose that sync1 and sync2 are actually sw1 and sw2

 

https://www.alteraforum.com/forum/attachment.php?attachmentid=13260
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