Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
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SignalTap: Start Rapid Recompile to continue

Altera_Forum
Honored Contributor II
3,410 Views

Hi, 

 

Why does the signal tap file not let me change the trigger condition? Every time I change the trigger condition, the signal tap says Start Rapid Recompile to continue. The nodes that I am trying to trigger on are all there. The lock mode is set to "Allow all changes" I am not sure why this occurs.
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Altera_Forum
Honored Contributor II
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If you don't want to recompile it each time you make a change I suggest you change the lock mode to "Allow trigger condition changes only". That way it'll only allow you to make changes that won't make changes to the design, requiring a recompile. 

 

Refer to Quartus' signaltap setup help page (http://quartushelp.altera.com/14.1/mergedprojects/program/ela/ela_tab_setup.htm) for some more detail. 

 

Cheers, 

Alex
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