SignalTap logging to external memory?

[Altera_Forum]

Hi, 

 Is it possible to get SignalTap to use external memory for data logging?   I got 256MByte of DDR2 memory in my NIOS system, using the Altera DDR2 memory controller. Logging traces to this memory could be usefull, when debugging slow but long signal patterns, e.g. a complete PAL/NTSC video frame signal.   BR Peter

[Altera_Forum]

--- Quote Start ---  Hi,   Is it possible to get SignalTap to use external memory for data logging?   I got 256MByte of DDR2 memory in my NIOS system, using the Altera DDR2 memory controller. Logging traces to this memory could be usefull, when debugging slow but long signal patterns, e.g. a complete PAL/NTSC video frame signal.   BR Peter  --- Quote End ---    Hi Peter,  as far as I know it is not possible to use an external memory for Signaltap. Maybe you can reduce the number of signals so that a frame fits into the internal memory ?   When you have access to FPGA pins on your board a Logic Analyzer could be an option. For a logic analyzer you can use the LAI (Logic Analyzer Inferface) feature or route the  required signals with "signalprobe" to the pins.  Tools -> Logic Analyzer Interface Editor  Tools -> Signalprobe pins

[Altera_Forum]

Peter, 

 I agree to pletz. As far as i know there is no way to connect external memory to signal tap. So, I would recommend that you built your own trace logic and write the data of interest into memory using a FIFO and a DMA controller.

[Altera_Forum]

DDR2 is going to have bandwidth issues. Hopefully too much, but if it's too little than the capture will fail. In-system memory works because only and exactly what is necessary will be used. More importantly, if the design had DDR2 on it, most likely the designer has their own controller and it's part of system operation(unless it's a development kit that happened to have DDR2 on it). So there's no way for SignalTap to access the DDR2 without altering the user's design.

[Altera_Forum]

SignalTap will not do it for you. 

 I have written a few internal logic analyzers that made use of DDR2 memory. You can certainly do it; especially to do simple captures comparable to what SignalTap does. But of course you will have to write all of the logic (memory interface, trigger logic).  Jake

[Altera_Forum]

jakobjones: 

 Yes, it was exactly that I wanted, captures which are of lower bandwide (compared to internal FPGA RAM), but with long sequences of signals.   If Altera had/made an IP that plug'ed on to the Avalon bus as a busmaster on one side, and to "probe-signals" on the other, any free bandwide on whatever RAM on the Avalon bus that is present, could be used for logging.    Doing the IP myself, will still miss the important integration with the SignalTap GUI in Quartus on the PC, so although making a FIFO+Avalon master DMA muck-up would not be a big problem, getting the data out of the RAM and presented on the PC in a usefull way would need some work, I think?   Hope Altera will do such a core/GUI integration one day.   /Peter

[Altera_Forum]

Quite right. For the projects I did, we also had to write the GUI. 

 Jake