Similation

[Okarin]

I have a project for cyclone 3. Can I send a verilogue code to the input of a circuit to get a simulation in modelSim?

[sstrell]

Yes.  A testbench is typically code that is written as a "wrapper" around your design under test (DUT) that provides stimulus to the inputs and optionally monitors the outputs.

[Okarin]

i created university program vwf, selected the required inputs and generated testbench. However, the file was created in .vwf.vht format, not .v

[Kenny_Tan · Accepted solution]

Those are just the created testbench files, you can copy it and save it as .v.

Unfortunately, you vwf files does not have a place for you to store the testbench. If you want to do that, you may have to use modelsim instead.

[Kenny_Tan]

Any further queries?

[Kenny_Tan]

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