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Beginner
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Similation

I have a project for cyclone 3. Can I send a verilogue code to the input of a circuit to get a simulation in modelSim?
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Moderator
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Yes.  A testbench is typically code that is written as a "wrapper" around your design under test (DUT) that provides stimulus to the inputs and optionally monitors the outputs.

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Beginner
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i created university program vwf, selected the required inputs and generated testbench. However, the file was created in .vwf.vht format, not .v
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